參數(shù)資料
型號(hào): XRT91L30IQTR-F
廠商: Exar Corporation
文件頁(yè)數(shù): 16/40頁(yè)
文件大?。?/td> 0K
描述: IC TXRX SONET/SDH 8BIT 64QFP
標(biāo)準(zhǔn)包裝: 1,000
類型: 收發(fā)器
規(guī)程: SONET/SDH
電源電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 64-FQFP
供應(yīng)商設(shè)備封裝: 64-PQFP(10x10)
包裝: 帶卷 (TR)
XRT91L30
19
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
2.10
Receive Parallel Data Output Timing
The receive parallel data output from the STS-12/STM-4 or STS-3/STM-1 receiver will adhere to the setup and
hold times shown in Figure 10 ,Table 8, and Table 9. Table 10 shows the PECL and TTL output timing
specifications.
FIGURE 10. RECEIVE PARALLEL OUTPUT TIMING
TABLE 8: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-12/STM-4 OPERATION)
TABLE 9: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-3/STM-1 OPERATION)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
tRXCLK
Receive high-speed serial clock period
1.608
ns
tRXPCLKO
Receive parallel data output byte clock period
12.86
ns
tRXDO_VALID
Time the data is valid on RXDO[7:0] and FRAMEPULSE
before and after the rising edge of RXPCLKO
4
ns
tPULSE_WID
Pulse width of frame detection pulse on FRAMEPULSE
12.86
ns
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
tRXCLK
Receive high-speed serial clock period
6.43
ns
tRXPCLKO
Receive parallel data output byte clock period
51.44
ns
tRXDO_VALID
Time the data is valid on RXDO[7:0] and FRAMEPULSE
before and after the rising edge of RXPCLKO
22
ns
tPULSE_WID
Pulse width of frame detection pulse on FRAMEPULSE
51.44
ns
tRXCLK
RXPCLKO
RXDO[7:0]
RXIP
RXIN
FRAMEPULSE
tRXDO_VALID
tRXPCLKO
A1
A2
tPULSE_WID
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