參數(shù)資料
型號(hào): XRT91L30IQTR-F
廠商: Exar Corporation
文件頁(yè)數(shù): 20/40頁(yè)
文件大?。?/td> 0K
描述: IC TXRX SONET/SDH 8BIT 64QFP
標(biāo)準(zhǔn)包裝: 1,000
類型: 收發(fā)器
規(guī)程: SONET/SDH
電源電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 64-FQFP
供應(yīng)商設(shè)備封裝: 64-PQFP(10x10)
包裝: 帶卷 (TR)
XRT91L30
23
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
3.3
Alternate Transmit Parallel Bus Clock Input Option
To decouple transmit parallel clock domains of the framer/mapper device and the XRT91L30 transceiver and to
eliminate difficult timing issues between them, the transmit parallel clock TXPCLK_IO can also be optionally
configured as a clock input. Rather than provide a transmit parallel clock output reference to the framer/mapper
device, the XRT91L30 can instead accept a reference transmit parallel clock input signal from the framer/
mapper device to sample the transmit parallel bus. When PIO_CTRL pin 48 is asserted "Low," TXPCLK_IO
switches into a clock input and the XRT91L30 will now sample data on the transmit parallel bus TXDI[7:0]
based on TXPCLK_IO clock input reference coming from the framer/mapper device. The use of the alternate
transmit parallel bus clock input option permits the system to tolerate an arbitrary amount of phase mismatch
and jitter between framer/mapper transmit parallel clock timing and transceiver transmit timing. Figure 13
provides a detailed overview of the alternate transmit parallel bus clock input system interface.
3.4
Alternate Transmit Parallel Data Input Timing
When applying parallel data input to the transmitter in the alternate transmit parallel bus clock input mode of
operation, the setup and hold times should be followed as shown in Figure 14 and Table 13, Table 14.
FIGURE 14. ALTERNATE TRANSMIT PARALLEL INPUT TIMING
FIGURE 13. ALTERNATE TRANSMIT PARALLEL INPUT INTERFACE BLOCK (PARALLEL CLOCK INPUT OPTION)
SONET Framer/ASIC
TXPCLK_IO
XRT91L30
STS-12/STM-4
or
STS-3/STM-1
Transceiver
TXDI[7:0]
8
(Parallel Clock Input Option)
REFCLKP
TTLREFCLK
CMUFREQSEL
REFCLKN
PIO_CTRL
tTXPCLK_IO
TXDI[7:0]
TXPCLK_IO
tTXDI_HD
tTXDI_SU
Alternate Transmit Parallel Clock Input Option
Transmit Parallel
Clock driven by
Framer/Mapper
Device
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