參數(shù)資料
型號： XRT91L30IQTR
廠商： Exar Corporation
文件頁數(shù)： 23/40頁
文件大?。?/td> 0K
描述： IC TXRX SONET/SDH 8BIT 64QFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 收發(fā)器
規(guī)程： SONET/SDH
電源電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 64-FQFP
供應(yīng)商設(shè)備封裝： 64-PQFP（10x10）
包裝： 帶卷 (TR)
XRT91L30
I
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
TABLE OF CONTENTS
NOTES:..................................................................................................................................................... II
GENERAL DESCRIPTION................................................................................................. 1
APPLICATIONS........................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF XRT91L30 ...................................................................................................................................... 1
FEATURES
..................................................................................................................................................... 2
FIGURE 2. 64 QFP PIN OUT OF THE XRT91L30 (TOP VIEW)............................................................................................................ 3
ORDERING INFORMATION .................................................................................................................... 3
TABLE 1: ........................................................................................................................................................................................ 4
PIN DESCRIPTIONS .......................................................................................................... 4
..................................................................................................................................................................... 4
HARDWARE CONTROL.................................................................................................................................... 4
TRANSMITTER SECTION.................................................................................................................................. 7
RECEIVER SECTION ....................................................................................................................................... 9
POWER AND GROUND .................................................................................................................................. 10
1.0 FUNCTIONAL DESCRIPTION ............................................................................................................. 12
1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ......................................................................... 12
1.2 CLOCK INPUT REFERENCE FOR CLOCK MULTIPLIER (SYNTHESIZER) UNIT ...................................... 12
TABLE 2: CMU REFERENCE FREQUENCY OPTIONS (DIFFERENTIAL OR SINGLE-ENDED) ................................................................... 12
1.3 DATA LATENCY ............................................................................................................................................. 12
TABLE 3: DATA INGRESS TO DATA EGRESS LATENCY ....................................................................................................................... 12
2.0 RECEIVE SECTION ............................................................................................................................. 13
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 13
FIGURE 3. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 13
2.2 RECIEVE SERIAL DATA INPUT TIMING ...................................................................................................... 14
FIGURE 4. RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING DIAGRAM .......................................................................................... 14
TABLE 4: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-12/STM-4 OPERATION) ............................................................. 14
TABLE 5: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-3/STM-1 OPERATION)............................................................... 14
2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15
TABLE 6: CLOCK DATA RECOVERY UNIT REFERENCE CLOCK SETTINGS ............................................................................................ 15
TABLE 7: CLOCK AND DATA RECOVERY UNIT PERFORMANCE.......................................................................................................... 15
2.3.1 INTERNAL CLOCK AND DATA RECOVERY BYPASS ............................................................................................ 16
FIGURE 5. INTERNAL CLOCK AND DATA RECOVERY BYPASS............................................................................................................ 16
2.4 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 16
FIGURE 6. EXTERNAL LOOP FILTERS .............................................................................................................................................. 16
2.5 LOSS OF SIGNAL .......................................................................................................................................... 16
FIGURE 7. LOS DECLARATION CIRCUIT........................................................................................................................................... 17
2.6 SONET FRAME BOUNDARY DETECTION AND BYTE ALIGNMENT RECOVERY .................................... 17
2.7 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 17
FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF SIPO ........................................................................................................................... 18
2.8 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 18
FIGURE 9. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK ............................................................................................................. 18
2.9 DISABLE PARALLEL RECEIVE DATA OUTPUT UPON LOS ..................................................................... 18
2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 19
FIGURE 10. RECEIVE PARALLEL OUTPUT TIMING ............................................................................................................................ 19
TABLE 8: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-12/STM-4 OPERATION) ......................................................................... 19
TABLE 9: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-3/STM-1 OPERATION) ........................................................................... 19
TABLE 10: PECL AND TTL RECEIVE OUTPUTS TIMING SPECIFICATION............................................................................................ 20
3.0 TRANSMIT SECTION .......................................................................................................................... 21
3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................ 21
FIGURE 11. TRANSMIT PARALLEL INPUT INTERFACE BLOCK............................................................................................................. 21
3.2 TRANSMIT PARALLEL DATA INPUT TIMING ............................................................................................. 22
FIGURE 12. TRANSMIT PARALLEL INPUT TIMING .............................................................................................................................. 22
TABLE 11: TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION)......................................................................... 22
TABLE 12: TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION)........................................................................... 22
3.3 ALTERNATE TRANSMIT PARALLEL BUS CLOCK INPUT OPTION .......................................................... 23
FIGURE 13. ALTERNATE TRANSMIT PARALLEL INPUT INTERFACE BLOCK (PARALLEL CLOCK INPUT OPTION) ...................................... 23
3.4 ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING ....................................................................... 23
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參數(shù)描述
XRT91L30IQTR-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT91L31 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L31_08 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L31ES 功能描述:總線收發(fā)器 RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L31IQ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SONET/SDH, FULL DPLX 3.3V I/O, LOS, CMU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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