參數(shù)資料
型號(hào): XRT91L30IQTR
廠商: Exar Corporation
文件頁數(shù): 24/40頁
文件大?。?/td> 0K
描述: IC TXRX SONET/SDH 8BIT 64QFP
標(biāo)準(zhǔn)包裝: 1,000
類型: 收發(fā)器
規(guī)程: SONET/SDH
電源電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 64-FQFP
供應(yīng)商設(shè)備封裝: 64-PQFP(10x10)
包裝: 帶卷 (TR)
XRT91L30
26
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.2
Table 16 provides configuration for selecting the loop timing and clock recovery modes. The use of the on-chip
CDR or an external recovered clock in loop timing applications is shown in Figure 16.
TABLE 16: LOOP TIMING AND CLOCK RECOVERY CONFIGURATIONS
CDRDIS
LOOPTIME
TRANSMIT CLOCK SOURCE
RECEIVE CLOCK SOURCE
0
Clock Multiplier Unit
CDR Enabled.
Clock and Data recovery by internal CDR
0
1
Internal CDR
CDR Enabled.
Clock and Data recovery by internal CDR
1
0
Clock Multiplier Unit
CDR Disabled.
Externally recovered Receive Clock from
XRXCLKIP/N
622.08/155.52 Mbps data on RXIP/N sampled at
rising edge of XRXCLKIP/N
1
External CDR thru XRXCLKIP/N
CDR Disabled.
Externally recovered Receive Clock from
XRXCLKIP/N
622.08/155.52 Mbps data on RXIP/N sampled at
rising edge of XRXCLKIP/N
FIGURE 16. LOOP TIMING MODE USING INTERNAL CDR OR AN EXTERNAL RECOVERED CLOCK
RXIP
RXIN
M
U
X
CDR
MUX
M
U
X
REFCLKP
REFCLKN
TTLREFCLK
CDRDIS
Div by 8
Clk
Data
~
XRT91L30
LOOPTIME
XRXCLKIP
XRXCLKIN
DATA
PISO
to Retimer
SIPO
Retimer
TXOP
TXON
CLK
8
RXDO[7:0]
RXPCLKO
DATA
CLK
TXPCLK_IO
PIO_CTRL
ENB
M
U
X
0
1
Div by
8
TXDI[7:0]
622.08/
155.52MHz
CMU
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