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參數(shù)資料
| 型號： | XRT91L31 |
| 廠商： | Exar Corporation |
| 英文描述： | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| 中文描述： | STS-12/STM-4或STS-3/STM-1的SONET / SDH收發(fā)器 |
| 文件頁數(shù)： | 19/41頁 |
| 文件大?。?/td> | 356K |
| 代理商： | XRT91L31 |
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xr
REV. 1.0.2
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
17
2.4
These external loop filter 0.47
μ
F non-polarized capacitors provide the necessary components to achieve the
required receiver jitter performance. They must be well isolated to prohibit noise entering the CDR block and
should be placed as close to the pins as much as possible. Figure 6 shows the pin connections and external
loop filter components. These two non-polarized capacitors should be of +/- 10% tolerance.
External Receive Loop Filter Capacitors
2.5
XRT91L31 supports internal Loss of Signal detection (LOS) and external LOS detection. The internal Loss of
Signal Detector monitors the incoming data stream and if the incoming data stream has no transition
continuously for more than 128 bit periods, Loss of Signal is declared. This LOS detection will be removed
when the circuit detects 16 transitions in a 128 bit period sliding window. Pulling the corresponding DLOSDIS
signal to a high level will disable the internal LOS detection circuit. The external LOS function is supported by
the LOSEXT input. The Single-Ended LVPECL input usually comes from the optical module through an output
usually called “SD” or “FLAG” which indicates the lack or presence of optical power. Depending on the
manufacturer of these devices, the polarity of this signal can be either active "Low" or active "High". LOSEXT is
an active "Low" signal requiring a low level to assert or invoke a forced LOS. The external LOSEXT input pin
and internal LOS detector are gated to control detection and declaration of Loss of Signal (see Figure 7.)
Whenever LOS is internally detected or an external LOS is asserted thru the LOSEXT pin, and none of the
local loopback loops is enabled, the XRT91L31 will automatically force the receive parallel data output to a
logic state "0" for the entire duration that a LOS condition is declared. This acts as a receive data mute upon
LOS function to prevent random noise from being misinterpreted as valid incoming data. When the local
Loss Of Signal
loopbacks DLOOP and ALOOP are enabled, then LOS conditions will not mute the RX parallel output.
F
IGURE
6. E
XTERNAL
L
OOP
F
ILTERS
F
IGURE
7. LOS D
ECLARATION
CIRCUIT
CAP2N
CAP1N
0.47uF
non-polarized
CAP2P
CAP1P
0.47uF
non-polarized
pin 42
pin 39
pin 40
pin 41
DLOS (internal signal)
DLOSDIS
LOSEXT’
ALOOP
DLOOP
‘0’ = No LOS detection =>
Do not mute receive
parallel data bus
‘1’ = LOS_detection =>
Mute Receive data bus
RLOOPS
RLPS_D_MUTE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT91L31IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L32 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L32IQ-F | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L80 | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L80_0507 | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L31_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L31ES | 功能描述:總線收發(fā)器 RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L31IQ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SONET/SDH, FULL DPLX 3.3V I/O, LOS, CMU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT91L31IQ-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8-Bit TTL 3.3V temp -45 to 85C;UART RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT91L31IQ-F | 制造商:Exar Corporation 功能描述:SONET Transceiver IC |
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