參數(shù)資料
型號: XRT91L31
廠商: Exar Corporation
英文描述: STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
中文描述: STS-12/STM-4或STS-3/STM-1的SONET / SDH收發(fā)器
文件頁數(shù): 27/41頁
文件大?。?/td> 356K
代理商: XRT91L31
xr
REV. 1.0.2
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
25
T
ABLE
12: A
LTERNATE
T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-12/STM-4 O
PERATION
)
T
ABLE
13: A
LTERNATE
T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-3/STM-1 O
PERATION
).
3.5
The PISO is used to convert 77.76 Mbps or 19.44 Mbps parallel data input to 622.08 Mbps STS-12/STM-1 or
155.52 Mbps STS-3/STM-1 serial data output respectively, which can interface to an optical module. The
PISO bit interleaves parallel data input into a serial bit stream taking the first bit from TXDI7, then the first bit
from TXDI6, and so on as shown in Figure 15.
Transmit Parallel Input to Serial Output (PISO)
S
YMBOL
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
t
TXPCLK_IO
Transmit Clock
Input
period
12.86
ns
t
TXDI_SU
Transmit data setup time with respect to TXPCLK_IO
1.0
ns
t
TXDI_HD
Transmit data hold time with respect to TXPCLK_IO
1.0
ns
S
YMBOL
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
t
TXPCLK_IO
Transmit Clock
Input
period
51.44
ns
t
TXDI_SU
Transmit data setup time with respect to TXPCLK_IO
1.0
ns
t
TXDI_HD
Transmit data hold time with respect to TXPCLK_IO
1.0
ns
F
IGURE
15. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
PISO
b
0
0
b
0
1
b
0
2
b
0
3
b
0
4
b
0
5
b
0
6
b
0
7
b
n
0
b
n
1
b
n
2
b
n
3
b
n
4
b
n
5
b
n
6
b
n
7
b
n+
0
b
n+
1
b
n+
2
b
n+
3
b
n+
4
b
n+
5
b
n+
6
b
n+
7
b
7
0
b
7
1
b
7
2
b
7
3
b
7
4
b
7
5
b
7
6
b
7
7
8-bit Parallel LVTTL Input Data
TXDI0
TXDI7
TXDIn+
TXDIn
TXOP/N
TXPCLK_IO
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
622.08 Mbps STS-12/STM-4 or
155.52 Mbps STS-3/STM-1 serial data rate
b
4
0
b
5
0
b
6
0
b
7
0
b
2
0
b
3
0
b
4
7
b
5
7
b
6
7
b
7
7
b
0
7
b
1
7
b
2
7
b
3
7
P
time (0)
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