參數(shù)資料
型號(hào)： XTR108
英文描述： 4-20mA, TWO-WIRE TRANSMITTER Smart Programmable with Signal Conditioning
中文描述： 的4 - 20mA，兩線制變送器可編程智能與信號(hào)調(diào)理
文件頁(yè)數(shù)： 14/27頁(yè)
文件大?。?/td> 497K
代理商： XTR108
XTR108
SBOS187B
14
www.ti.com
Address = 5: Over- and Under-Scale Register
This register sets the magnitude of the over-scale current
limit and the magnitude of the under-scale current limit. The
threshold level, as shown in Table VII and VIII, is the
normal analog (no error condition) output limit. If an input
voltage to the PGA exceeds the linear operation range, the
output will be programmed to either the over-scale error
level or the under-scale error level. The over-scale error
level is 10mA greater than the over-scale threshold level.
The under-scale error level is 0.4mA less than the under-
scale threshold level. The FD bit will disable the over-scale
and under-scale limiting function as well as the PGA fault
indication error levels.
Address = 6: PGA Gain Register
This register sets the gain of the programmable-gain ampli-
fier. The unused bits must always be set to ‘0’. The gain step
to register content is given in Table IX.
Address = 7: Alarm Configuration Register
This register configures whether the XTR108 will go over-
scale or under-scale for various detected fault conditions at
the input of the PGA. Table X defines each of the bits.
If a bit corresponding to the particular error is set to ‘1’, the
output will go over-scale when it occurs and if a bit corre-
sponding to the particular error is set to ‘0’, the output will
go under-scale.
Address = 8: PGA Input Configuration Register
This register connects the inputs of the PGA to the various
multiplexed input pins. Tables XI and XII show the relation-
ship between register, contents, and PGA inputs.
Address = 9: I
REF
Output Configuration Register
This register connects the reference currents to the various
multiplexed input pins. I
REF
connection codes are given in
Table XIII.
Address = 10: Fine I
REF
Adjust Register
This register sets the code to the 8-bit Fine DAC that adjusts
the magnitude of both reference currents. The DAC output
value has a bipolar range (for each reference current) and
can be calculated using the equations in Table III.
I
O
UNDER-SCALE
THRESHOLD
R
VI
= 6.34k
V
O
UNDER-SCALE
THRESHOLD
US2
US1
US0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
450mV
425mV
400mV
375mV
350mV
325mV
300mV
275mV
3.55mA
3.35mA
3.15mA
2.96mA
2.76mA
2.56mA
2.37mA
2.17mA
TABLE VIII. Register 5, Under-Scale Threshold.
I
O
OVER-SCALE
THRESHOLD
R
VI
= 6.34k
V
O
OVER-SCALE
THRESHOLD
OS3
OS2
OS1
OS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.625V
2.6875V
2.75V
2.8125V
2.875V
2.9375V
3.0V
3.0625V
3.125V
3.1875V
3.25V
3.3125V
3.375V
3.4375V
3.5V
3.5625V
20.7mA
21.2mA
21.7mA
22.2mA
22.7mA
23.2mA
23.7mA
24.2mA
24.6mA
25.1mA
25.6mA
26.1mA
26.6mA
27.1mA
27.6mA
28.1mA
TABLE VII. Register 5, Over-Scale Threshold.
SIGNAL PATH
TRANSCONDUCTANCE
R
VI
= 6.34k
PGA
G2
G1
G0
VOLTAGE GAIN
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6.25V/V
12.5V/V
25V/V
50V/V
100V/V
200V/V
400V/V
Reserved
49mA/V
99mA/V
197mA/V
394mA/V
789mA/V
1577mA/V
3155mA/V
TABLE IX. Register 6, PGA Gains.
BIT
AC
AC
AC
AC
AC
AC
AC
AC
#
7
h
l
6
l
h
5
l
l
4
h
h
3
n
l
2
n
h
1
l
n
0
h
n
V
INN
V
INP
NOTES:
‘
h
’
= input exceeds positive common-mode range,
‘
l
’
= input exceeds
negative common-mode range, and
‘
n
’
= input pin is within the CM range.
TABLE X. Register 7, Alarm Configuration Register.
VP2
VP1
VP0
PGA POSITIVE INPUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PGA V
IN+
Connected to V/I-0
PGA V
IN+
Connected to V/I-1
PGA V
IN+
Connected to V/I-2
PGA V
IN+
Connected to V/I-3
PGA V
IN+
Connected to V/I-4
PGA V
IN+
Connected to V/I-5
Reserved
Reserved
TABLE XI. Register 8, PGA Positive Input Selection.
VN2
VN1
VN0
PGA NEGATIVE INPUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PGA V
IN
–
Connected to V/I-0
PGA V
IN
–
Connected to V/I-1
PGA V
IN
–
Connected to V/I-2
PGA V
IN
–
Connected to V/I-3
PGA V
IN
–
Connected to V/I-4
PGA V
IN
–
Connected to V/I-5
Reserved
Reserved
TABLE XII. Register 8, PGA Negative Input Selection.
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