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參數資料
| 型號： | YSS922-S |
| 元件分類： | 噪聲抑制 |
| 英文描述： | DOLBY NOISE REDUCTION IC, PQFP128 |
| 封裝： | PLASTIC, SQFP-128 |
| 文件頁數： | 5/22頁 |
| 文件大?。?/td> | 298K |
| 代理商： | YSS922-S |
YSS922
13
2. Control Register / Register Map
The decoding system is controlled by reading and writing the control registers as shown below through
microprocessor interfaces (/CS, SCK, SI, SO).
All bits are set to “0” by initial clear (/IC= “L”).
Address
Name
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0x00
AUTO/DSN
AUTOMOD
PD1-0
DSNIGN
DSN2-0
0x01
MUTE
LMUTEN
CMUTEN
RMUTEN
RSMUEN
LSMUTEN LFEMUTEN DSPMUTEN
AMOFF
0x02
SDIA
SDIACKSEL
SDIASEL
SDIAFMT1-0
SDIABIT1-0
SDIAWP
SDIABP
0x03
SDOA
SDOAFMT1-0
SDOABIT1-0
SDOAWP
SDOABP
0x04
OPORT
OPORT7-0
0x05
IPORT
IPORT7-0
0x06
(TEST)
0x07
(TEST)
0x08
PCM
PCMDLY
0x09
NOISE LEVEL
NOISELEV7-0
0x0A
CENTER DELAY
CDELAY2-0
0x0B
SURROUND DELAY
SRDELAY3-0
0x0C
NOISE
PN/WN
IMPULSE
0x0D
FS
FS2-0
0x0E
L VOLUME
LVOL7-0
0x0F
C VOLUME
CVOL7-0
0x10
R VOLUME
RVOL7-0
0x11
LS VOLUME
LSVOL7-0
0x12
RS VOLUME
RSVOL7-0
0x13
LFE VOLUME
LFEVOL7-0
0x14
COMPRESSION
EMPON
AIBON
VOLON
DITHOFF
P11OFF
DIALOFF
COMPMOD1-0
0x15
HDYNRNG
HDYNRNG7-0
0x16
LDYNRNG
LDYNRNG7-0
0x17
MODE
PCMMOD PLDECON PLSRMOD
DUALMOD1-0
OUTMOD2-0
0x18
|
0x2A
BITSTREAM
(described in the later section)
0x2B
(Unused)
(Undefined)
0x2C
(Unused)
(Undefined)
0x2D
Pc
Pc7-0
0x2E
DATA STREAM
STREAM7 STREAM6 STREAM5 STREAM4 STREAM3 STREAM2 STREAM1 STREAM0
0x2F
STATUS
DTSDATA AC3DATA 2/0MODE
SURENC
KARAOKE
MUTE
CRC
NONPCM
0x30
ZERO
ZEROFLG
ZERO6-0
0x31
(TEST)
0x32
MPCNT_H
MPLOAD MPCLEARN
MPCNT11-8
0x33
MPCNT_L
MPCNT7-0
0x34
SDIB
SDIBCKSEL
SDIBSEL
SDIBFMT1-0
SDIBBIT1-0
SDIBWP
SDIBBP
0x35
SDOB
SDOBCKSEL
SDOBFMT1-0
SDOBBIT1-0
SDOBWP
SDOBBP
0x36
ERAM
OVFSEL
JMPSEL
RASREF ERAMMOD
ERAMSEL1-0
0x37
(TEST)
0x38
MI0
MI0REG7-0
0x39
MI1
MI1REG7-0
0x3A
MI2
MI2REG7-0
0x3B
MI3
MI3REG7-0
0x3C
MI4
MI4REG7-0
0x3D
MI5
MI5REG7-0
0x3E
MI6
MI6REG7-0
0x3F
MI7
MI7REG7-0
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