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參數(shù)資料
| 型號： | Z86C31 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CMOS Z8 CONSUMER CONTROLLER PROCESSOR |
| 中文描述： | 消費(fèi)者的CMOS Z8控制器處理器 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 128K |
| 代理商： | Z86C31 |
CP96DZ82900
13
Z86C30/C31/C32/C40
CP96DZ82900
Z
ILOG
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Table (Z86C40 Only)
(SCLK/TCLK = XTAL/2)
T
=–40
°
C to 105
°
C
12 MHz
Min Max
T
A
= –40
°
C to +105
°
C
12 MHz
Min Max Min Max
Note [3]
V
CC
16 MHz
Min Max
16 MHz
No Symbol Parameter
Units
Notes
1 TdA(AS)
Address Valid to /AS Rise Delay
3.0
5.5
3.0
5.5
35
35
45
45
25
25
35
35
35
35
45
45
25
25
35
35
ns
ns
ns
ns
[2]
2 TdAS(A)
/AS Rise to Address Float Delay
[2]
3 TdAS(DR)
/AS Rise to Read Data Reqd Valid
3.0
5.5
3.0
5.5
250
250
180
180
250
250
180
180
ns
ns
ns
ns
[1,2]
4 TwAS
/AS LowWidth
55
55
40
40
55
55
40
40
[2]
5 TdAS(DS)
Address Float to /DS Fall
3.0
5.5
3.0
5.5
0
0
0
0
0
0
0
0
ns
ns
ns
ns
6 TwDSR
/DS (Read) LowWidth
200
200
135
135
200
200
135
135
[1,2]
7 TwDSW
/DS (Write) LowWidth
3.0
5.5
3.0
5.5
110
110
80
80
110
110
80
80
ns
ns
ns
ns
[1,2]
8 TdDSR(DR) /DS Fall to Read Data Reqd Valid
150
150
75
75
150
150
75
75
[1,2]
9 ThDR(DS)
Read Data to /DS Rise Hold Time
3.00
5.5
3.0
5.5
0
0
45
55
0
0
50
50
0
0
45
55
0
0
50
50
ns
ns
ns
ns
[2]
10 TdDS(A)
/DS Rise to Address Active Delay
[2]
11 TdDS(AS)
/DS Rise to /AS Fall Delay
3.0
5.5
3.0
5.5
30
45
45
45
35
35
25
25
30
45
45
45
35
55
25
25
ns
ns
ns
ns
[2]
12 TdR/W(AS) R//W Valid to /AS Rise Delay
[2]
13 TdDS(R/W) /DS Rise to R//W Not Valid
3.0
5.5
45
45
55
55
35
35
25
25
45
45
55
55
35
35
25
25
ns
ns
ns
ns
[2]
14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 3.0
[2]
5.5
15 TdDS(DW) /DS Rise to Write Data Not Valid Delay
3.0
5.5
3.0
5.5
45
45
35
35
45
45
35
35
ns
ns
ns
ns
[2]
16 TdA(DR)
Address Valid to Read Data Reqd Valid
310
310
230
230
310
310
230
230
[1,2]
17 TdAS(DS)
/AS Rise to /DS Fall Delay
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
65
65
35
35
45
45
45
45
45
45
30
30
35
35
35
35
65
65
35
35
45
45
45
45
45
45
30
30
35
35
35
35
ns
ns
ns
ns
ns
ns
ns
ns
[2]
18 TdDM(AS) /DM Valid to /AS Fall Delay
[2]
19 TdDS(DM) /DS Rise to DM Valid Delay
20 ThDS(AS)
/DS Valid to Address Valid Hold Time
Notes:
[1] When using extended memory timing add 2 TpC.
[2] Timing numbers given are for minimum TpC.
[3] The V
voltage specification of 3.0V guarantees 3.3V
±
0.3V, and the
V
DD
voltage specification of 5.5V guarantees 5.0V
±
0.5V.
Standard Test Load
All timing references use 0.7 V
for a logic 1 and 0.2 V
for a logic 0.
For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0,
D0 = 0.
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