參數(shù)資料
型號: Z86C31
廠商: ZiLOG, Inc.
英文描述: CMOS Z8 CONSUMER CONTROLLER PROCESSOR
中文描述: 消費者的CMOS Z8控制器處理器
文件頁數(shù): 7/17頁
文件大?。?/td> 128K
代理商: Z86C31
CP96DZ82900
7
Z86C30/C31/C32/C40
CP96DZ82900
Z
ILOG
ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Units
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin with Respect to V
SS
[Note 1]
Voltage on V
Pin with Respect to V
Voltage on XTAL1 and /RESET Pins with Respect to V
SS
[Note 2]
Total Power Dissipation
Maximum Allowable Current out of V
SS
Maximum Allowable Current into V
Maximum Allowable Current into an Input Pin [Note 3]
Maximum Allowable Current into an Open-Drain Pin [Note 4]
Maximum Allowable Output Current Sinked by Any I/O Pin
Maximum Allowable Output Current Sourced by Any I/O Pin
–40
–65
–0.6
–0.3
–0.6
+105
+150
+7
+7
V
+1
1.21
220
180
+600
+600
25
25
C
C
V
V
V
W
mA
mA
μ
A
μ
A
mA
mA
–600
–600
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to Ground.
Positive current flows into the referenced pin (Test Load).
CAPACITANCE
T
A
= 25
°
C, V
CC
= GND = 0V, f = 1.0 MHz; unmeasured pins returned to GND.
Parameter
Min
Max
Input capacitance
Output capacitance
I/O capacitance
0
0
0
12 pF
12 pF
12 pF
Notes:
[1] This applies to all pins except XTAL pins and where otherwise noted.
[2] There is no input protection diode from pin to V
DD
.
[3] This excludes XTAL pins.
[4] Device pin is not at an output Low state.
Total power dissipation should not exceed 1.21 W for the
package. Power dissipation is calculated as follows:
Total Power Dissipation = V
x [ I
– (sum of I
OH
) ]
+ sum of [ (V
DD
– V
OH
) x I
OH
]
+ sum of (V
0L
0L
)
Notice:
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; functional operation of the
device at any condition above those indicated in the
operational sections of these specifications is not implied.
Exposure to absolute maximum rating conditions for an
extended period may affect device reliability.
From Output
Under Test
150 pF
Test Load Diagram
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