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| 型號： | Z86C34 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CMOS Z8 MCU(CMOS Z8系列微控制器) |
| 中文描述： | 單片機的CMOS Z8的CMOS（Z8系列微控制器） |
| 文件頁數(shù)： | 52/70頁 |
| 文件大?。?/td> | 1192K |
| 代理商： | Z86C34 |
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Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
52
P R E L I M I N A R Y
DS007601-Z8X0499
ASCI EXTENSION CONTROL REGISTER (ASEXT)
(%(A)05H: READ/WRITE)
BIT 7 is the RX State (READ ONLY)
Provides the real time state of
RX
, the channel’s receive data
input pin—
P30
.
BIT 6 is Reserved
When read, this bit reflects the default value
0
. When
WRITE
, this bit is ignored.
Bit 5 is Reserved
When read, this bit reflects the default value
0
. When
WRITE
, this bit is ignored
.
Bit 4 is the X1 Bit Clock
Reserved—must be set to
0
or erratic results may occur.
Bit 3 is the BRG Mode
When this bit is set to a
1
, the ASCI’s baud rate is set by
the 16-bit programmable divider programmed in ASCI
Time Constant High
(ASTH
) and ASCI Time Constant Low
(
ASTL
). If this bit is set to a
0
, the baud rate is defined by
the
PR
bit, the
DR
bit, and the
SS2–0
bits in the
CNTLB
reg-
ister. In either case, the source for the baud rate generator
is the
SCLK
. See the
Baud Rate Generation Summary
for
more information on setting the ASCI baud rate.
Bit 2 is the Rx Interrupt on Start
If software sets this bit to
1
,a receive interrupt is requested
(in a combinatorial fashion) when a
START
bit is detected
on
RX
. Such a receive interrupt is always followed by the
setting of
RDRF
in the middle of the
STOP
bit. This interrupt
request must be cleared by writing this bit back to a
0
. Writ-
ing a
1
to this bit has no effect. One function of this feature
is to wake the part from Sleep mode when a character ar-
rives, so that the ASCI receives clocking with which to pro-
cess the character. Another function is to ensure that the as-
sociated interrupt service routine is activated in time to
sense the setting of
RDRF
in the status register, and to start
a timer for baud rate measurement at that time.
Bit 1 is the Break Detect (READ ONLY)
This status bit is set to a
1
when a Break is detected, defined
as a framing error with the data bits all equal to
0
. The all-
zero byte with its associated error bits are transferred to the
FIFO if it is not full. If the FIFO is full, an overrun is gen-
erated, but the break, framing error and data are not trans-
ferred to the FIFO. Any time a break is detected, the receiver
do not receive any more data until the
RX
pin returns to a
High state. When set, this bit remains set until it is cleared
by writing a
0
to the
EFR
bit in the
CNTLA
register.
Bit 0 is the Send Break
Setting this bit to a
1
forces the channel’s transmitter data
output pin,
TX
, to a Low for as long as it remains set. Before
starting the break, any character(s) in the
TSR
and in the
TDR
are completely transmitted. If a character is loaded into
the
TDR
while a break is being generated, that character is
held until the break is terminated and transmitted.
Table 23. ASEXT Register Bit Functions
Bit
7
6
5
4
3
2
1
0
R
RX State
(RX)
Reserved
Reserved
Reserved
(must be 0)
BRG Mode
(BRGM)
RX
Interrupt on
Start Bit
(RIS)
Break
Detect
(BD)
Send Break
(SB)
W
Reset
P30
0
0
0
0
0
0
0
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