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參數(shù)資料
| 型號： | Z86C35 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CMOS Z8 MCU(CMOS Z8系列微控制器) |
| 中文描述： | 單片機的CMOS Z8的CMOS（Z8系列微控制器） |
| 文件頁數(shù)： | 37/70頁 |
| 文件大?。?/td> | 1192K |
| 代理商： | Z86C35 |
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Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
DS007601-Z8X0499
P R E L I M I N A R Y
37
Power-On-Reset (POR).
A timer circuit clocked by a ded-
icated on-board RC oscillator is used for the Power-On Re-
set (
POR
) timer function. The
POR
time allows
V
CC
and the
oscillator circuit to stabilize before instruction execution
begins.
The
POR
timer circuit is a one-shot timer triggered by one
of three conditions:
1. Power fail to Power OK status.
2. Stop-Mode Recovery (if
D5
of
SMR = 1
).
3.
WDT
time-out.
The
POR
time is specified as
T
POR
. Bit
5
of the Stop-Mode
Register determines whether the
POR
timer is bypassed af-
ter Stop-Mode Recovery (typical for external clock,
RC
/
LC
oscillators).
HALT.
HALT
turns off the internal CPU clock, but not the
XTAL
oscillation. The counter/timers and external inter-
rupts
IRQ0
,
IRQ1
,
IRQ2
, and
IRQ3
remain active. The de-
vices are recovered by interrupts and are either externally
or internally generated. An interrupt request must be en-
abled and executed to exit
HALT
mode. After the interrupt
service routine, the program continues from the instruction
after the
HALT
.
In order to enter
STOP
(or
HALT
) mode, it is necessary to
first flush the instruction pipeline to avoid suspending ex-
ecution in mid-instruction. Therefore, the user must execute
a
NOP
(Op Code =
FFH
) immediately before the appropriate
sleep instruction. For example:
STOP.
This instruction turns off the internal clock and ex-
ternal crystal oscillation. It also reduces the standby current
to 10 μA or less. The
STOP
mode is terminated by a
RESET
only, either by
WDT
time-out,
POR
,
SMR
recovery, or ex-
ternal reset. As a result, the processor restarts the applica-
tion program at address
000Ch
. A
WDT
time-out in
STOP
mode affects all registers the same as if a Stop-Mode Re-
covery occurred via a selected Stop-Mode Recovery source
except that the
POR
delay is enabled even if the delay is se-
lected for disable.
Note:
If a permanent
WDT
is selected, the
WDT
runs in all
modes and cannot be stopped or disabled if the onboard
RC
oscillator is selected to drive the
WDT
.
Port Configuration Register (PCON).
The
PCON
regis-
ter configures the ports individually; comparator output on
Port 3, open-drain on Port 0 and Port 1, low EMI on Ports
Figure 24. Oscillator Configuration
XTAL1
XTAL2
C1
C2
C1
C2
C1
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
Ceramic Resonator or
Crystal
C1, C2 = 47 pF TYP *
f = 8 MHz
LC
C1, C2 = 22 pF
L = 130 uH *
f = 3 MHz *
RC
@ 5V V (TYP)
C1 = 33 pF *
R = 1K *
f = 6 MHz *
External Clock
L
R
*Preliminary value including pin parasitics
**Device ground pin
V **
V **
V **
V **
V **
FF
6F
NOP
STOP
; clear the pipeline
; enter STOP mode
or
; clear the pipeline
; enter HALT Mode
FF
7F
NOP
HALT
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