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參數(shù)資料
| 型號(hào)： | Z86C35 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CMOS Z8 MCU(CMOS Z8系列微控制器) |
| 中文描述： | 單片機(jī)的CMOS Z8的CMOS（Z8系列微控制器） |
| 文件頁數(shù)： | 40/70頁 |
| 文件大?。?/td> | 1192K |
| 代理商： | Z86C35 |
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Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
40
P R E L I M I N A R Y
DS007601-Z8X0499
FUNCTIONAL DESCRIPTION
(Continued)
Stop-Mode Recovery Delay Select (D5).
This bit, if
High, enables the
T
POR
RESET
delay after Stop-Mode Re-
covery. The default configuration of this bit is
1
. If the
fast
wake up is selected, the Stop-Mode Recovery source must
be kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select (D6).
A
1
in this bit
position indicates that a high level on any one of the recov-
ery sources wakes the Z8 from
STOP
mode. A
0
indicates
low-level recovery. The default is
0
on
POR
(Figure 28).
This bit is used for either
SMR
or
SMR2
.
Cold or Warm Start (D7).
This bit is set by the device
upon entering
STOP
mode. A
0
in this bit (cold) indicates
that the device resets by
POR
/
WDT
RESET
. A
1
in this bit
(warm) indicates that the device awakens by a Stop-Mode
Recovery source.
Note:
If the Port 2 pin is configured as an output, this output
level is read by the
SMR2
circuitry.
Figure 28. Stop-Mode Recovery Source
P30
P31
P32
P33
P27
Stop-Mode Recovery Edge
Select (SMR)
P33 From Pads
Digital/Analog Mode
Select (P3M)
To P33 Data
Latch and IRQ1
To POR
RESET
SMR
SMR
SMR
D4 D3 D2
0 0 1
0 1 0
0 1 1
D4 D3 D2
1 0 0
D4 D3 D2
1 0 1
MUX
SMR
SMR
D4 D3 D2
1 1 0
D4 D3 D2
1 1 1
P20
P23
P20
P27
SMR2
SMR2
D1 D0
1 1
D1 D0
1 1
P20
P23
P20
P27
SMR
D4 D3 D2
0 0 0
V
DD
SMR2 D1 D0
0 0
V
DD
Table 13. Stop-Mode Recovery Source
SMR:432
D4 D3 D2
Operation
Description of Action
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
POR and/or external reset recovery
P30 transition
P31 transition (not in Analog Mode)
P32 transition (not in Analog Mode)
P33 transition (not in Analog Mode)
P27 transition
Logical NOR of P20 through P23
Logical NOR of P20 through P27
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