
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
36
P R E L I M I N A R Y
DS007601-Z8X0499
FUNCTIONAL DESCRIPTION
(Continued)
An interrupt resulting from
AN1
maps to
IRQ2
, and an in-
terrupt from
AN2
maps to
IRQ0
. Interrupts
IRQ2
and
IRQ0
may be rising, falling, or both edge-triggered, and are pro-
grammable by the user. The software may poll to identify
the state of the pin. When in analog mode, the
IRQ1
gener-
ates by the Stop-Mode Recovery source selected by
SMR
Reg. bits
D4
,
D3
,
D2
, or
SMR2
D1
or
D0
.
Programming bits for the Interrupt Edge Select are located
in the IRQ register (
R250
), bits
D7
and
D6
. The configura-
tion is indicated in Table 12.
Clock.
The Z8 on-chip oscillator features a high-gain, par-
allel-resonant amplifier for connection to a crystal,
LC
,
RC
,
ceramic resonator, or any suitable external clock source
(
XTAL1 = INPUT
,
XTAL2 = OUTPUT
). The crystal should
be AT-cut, 16 MHz maximum, with a series resistance (
RS
)
of less than or equal to 100 Ohms when counting from
1 MHz to 16 MHz.
The crystal should be connected across
XTAL1
and
XTAL2
using the vendor’s recommended capacitor values from
each pin directly to the device Ground pin to reduce ground-
noise injection into the oscillator. The
RC
oscillator option
is mask-programmable on the Z8 and is selected by the cus-
tomer at the time when the ROM code is submitted.
Notes:
The
RC
option is available up to 8 MHz. The
RC
oscillator configuration must be an external resistor
connected from
XTAL1
to
XTAL2
, with a frequency-
setting capacitor from
XTAL1
to Ground (Figure 24).
For better noise immunity, the capacitors should be tied
directly to the device Ground pin (
V
SS
).
Table 12. IRQ Register
IRQ
Interrupt Edge
D7
0
0
1
1
D6
0
1
0
1
P31
F
F
R
R/F
P32
F
R
F
R/F
Notes:
F = Falling Edge
R = Rising Edge