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| 型號： | Z86C45 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CMOS Z8 MCU(CMOS Z8系列微控制器) |
| 中文描述： | 單片機的CMOS Z8的CMOS（Z8系列微控制器） |
| 文件頁數(shù)： | 44/70頁 |
| 文件大?。?/td> | 1192K |
| 代理商： | Z86C45 |
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Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
44
P R E L I M I N A R Y
DS007601-Z8X0499
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (ASCI)
Key features of the ASCI include:
Full-duplex operation
Programmable data format
7 or 8 data bits with optional ninth bit for multiprocessor
communication
P30
and
P37
can be used as general-purpose I/O as long
as the ASCI channels are disabled
One or two
STOP
bits
Odd, even or no parity
Programmable interrupt conditions
Four level data/status FIFOs for the receiver
Receive parity, framing and overrun error detection
Break detection and generation
Transmit Data Register.
Data written to the ASCI Trans-
mit Data Register (
TDR
) is transferred to the Transmit Shift
Register(
TSR
) as soon as the
TSR
is empty. Data can be
written while the
TSR
is shifting out the previous byte of
data, providing double buffering for the transmit data. The
TDR
is
READ
- and
WRITE
-accessible. Reading from the
TDR
does not affect the ASCI data transmit operation cur-
rently in progress.
Transmit Shift Register.
When the ASCI Transmit Shift
Register (
TSR
) receives data from the ASCI Transmit Data
Register, the data is shifted out to the
TX
(
P37
) pin. When
transmission is completed, the next byte (if available) is au-
tomatically loaded from the
TDR
into the
TSR
and the next
transmission starts. If no data is available for transmission,
the
TSR
idles at a continuous High level. This register is
not program-accessible.
Receive Shift Register.
When the
RE
bit is set in the
CNTLA
register, the
RX
(
P30
) pin is monitored for a Low.
One-half bit-time after a Low is sensed at
RX
, the ASCI
samples
RX
again. If
RX
goes back to High, the ASCI
ignores the previous Low and resumes looking for a new
Low, but if
RX
is still Low, it considers
RX
a
START
bit
and proceeds to clock in the data based upon the selected
baud rate. The number of data bits, parity, multiprocessor
and
STOP
bits are selected by the
MOD2
,
MOD1
,
MOD0
and multiprocessor mode (
MP
) bits in the
CNTLA
and
CNTLB
registers.
After the data is received, the appropriate
MP
, parity and
one
STOP
bit are checked. Data and any errors are clocked
into the receive data and status FIFO during the
STOP
bit
if there is an empty position available. Interrupts and Re-
ceive Data Register Full Flag also goes active during this
time. If there is no space in the FIFO at the time that the
RSR
attempts to transfer the received data into it, an overrun
error occurs.
Receive Data FIFO.
When a complete incoming data byte
is assembled in the
RSR
, it is automatically transferred to
the 4-byte FIFO, which serves to reduce the incidence of
overrun errors. The top (oldest) character in the FIFO (if
any) can be read via the Receive Data Register (
RDR
).
The next incoming data byte can be shifted into the
RSR
while the FIFO is full, thus providing an additional level of
buffering. However, an overrun occurs if the receive FIFO
is still full when the receiver completes assembly of that
character and is ready to transfer it to the FIFO. If this sit-
uation occurs, the overrun error bit associated with the pre-
vious byte in the FIFO is set. The latest data byte is not trans-
ferred from the shift register to the FIFO in this case, and
is lost. When an overrun occurs, the receiver does not place
any further data in the FIFO until the most recent good byte
received arrives at the top of the FIFO and sets the Overrun
latch, and software then clears the Overrun latch by a
WRITE
of
0
to the
EFR
bit. Assembly of bytes continues in
the shift register, but this data is ignored until the byte with
the overrun error reaches the top of the FIFO and the status
is cleared.
When a break occurs (defined as a framing error with the
data equal to all zeros), the all-zero byte with its associated
error bits are transferred to the FIFO if it is not full and the
Break Detect bit in the
ASEXT
register is set. If the FIFO
is full, an overrun is generated, but the break, framing error
and data are not transferred to the FIFO. Any time a break
is detected, the receiver does not receive any more data until
the
RX
pin returns to a high state.
If the channel is set in multiprocessor mode and the
MPE
bit of the
CNTLA
register is set to
1
,then break, errors and
data are ignored unless the MP bit in the received character
is a
1
. The two conditions listed above could cause the miss-
ing of a break condition if the FIFO is full and the break
occurs or if the MP bit in the transmission is not a one with
the conditions specified above.
ASCI Status FIFO/Registers.
This FIFO contains Parity
Error, Framing Error,
RX
Overrun, and Break status bits as-
sociated with each character in the receive data FIFO. The
status of the oldest character (if any) can be read from the
ASCI status register, which also provides several other,
non-FIFOed status conditions.
The outputs of the error FIFO go to the set inputs of soft-
ware-accessible error latches in the status register. Writing
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