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參數(shù)資料
| 型號(hào)： | Z86C8416VEC |
| 廠商： | ZILOG INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Z8 MCU MICROCONTROLLERS |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 28/46頁 |
| 文件大小： | 957K |
| 代理商： | Z86C8416VEC |
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Z86C83/C84
Z8
MCU Microcontrollers
28
DS96DZ80203
Analog-to-Digital Converter
The Analog-to-Digital (ADC) is an 8-bit half flash converter
that uses two reference resistor ladders for its upper 4 bits
(MSBs) and lower 4 bits (LSBs) conversion. Two reference
voltage pins, AV
and A
, are provided for external
reference voltage supplies. During the sampling period
from one of the eight channel inputs, the converter is also
being auto-zeroed before starting the conversion. The
conversion time is dependent on the internal clock
frequency. The minimum conversion time is 35 X
SCLK(see Figure 22).
The ADC is controlled by the Z8
and its three registers
(two Control and one Result) are mapped into the
Extended Register File. A conversion can be initiated by
writing to the ADC Control Register 0 after the ADC
Control Register 1 is configured.
The start command is implemented in such a way as to
begin a conversion at any time, if a conversion is in
progress and a new start command is received, then the
conversion in progress will be aborted and a new
conversion will be initiated. This allows the programmed
values to be changed without affecting a conversion-in-
progress. The new values will take effect only after a new
start command is received.
The ADC can be disabled (for low power) or enabled by a
Control Register bit.
Though the ADC will function for a smaller input voltage
and voltage reference, the noise and offsets remain
constant over the specified electrical range. The errors of
the converter will increase and the conversion time may
also take slightly longer due to smaller input signals.
ADC Calibration Offset
Specially matched resistors are program-enabled to allow
35.0 percent or 50 percent offset from A
. They may
selectively enable these resistors to offset the A
by 35.0
percent (2.5V to 5V) or 50 percent (1.75V to 5V) thereby
allowing the 8-bit ADC across a narrower voltage range.
This will allow significant resolution improvement within
the reduced voltage range.
Note:
The AV
must be the same value as V
CC
and A
GND
must be the same value as GND.
Figure 22. ADC Architecture
Start
Converter
A/D
Control
Reg.
8
8
A/D
Result
Reg.
ADR1
A/D
Converter
AV
CC
A
GND
A/D
Control
Reg.
ADC1
8
Selected
Channel
EXT
Sample
and
Hold
ADC Register
9
D4, D5
4
Calibration Offset
ADC0
Vref +
Vcc
Vref -
GND
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