參數(shù)資料
型號(hào)： Z86C96
廠(chǎng)商： ZiLOG, Inc.
英文描述： CMOS Z8 MICROCONTROLLER
中文描述： 單片機(jī)的CMOS Z8
文件頁(yè)數(shù)： 12/46頁(yè)
文件大?。?/td> 388K
代理商： Z86C96
12
Z86C61/62/96
Z8
M
ICROCONTROLLER
PIN DESCRIPTION
(Continued)
Table 6. Z86C96 68-Pin PLCC Pin Identification
Pin #
Symbol
Function
Direction
1-2
3
4
5
6
P44-P43
V
P45
XTAL2
XTAL1
Port 4, Pins 3,4
Power Supply
Port 4, Pin 5
Crystal, Oscillator Clock
Crystal, Oscillator Clock
In/Output
Input
In/Output
Output
Input
7
8
9
10
11
P37
P30
/RESET
R//W
/P0DS
Port 3, Pin 7
Port 3, Pin 0
Reset
Read/Write
Port 0 Data Strobe
Output
Input
Input
Output
Output
12
13-14
15
16
17
/DS
P47-P46
/P1DS
/AS
/DTIMER
Data Strobe
Port 4, Pins 6,7
Port 1 Data Strobe
Address Strobe
Disable Timers
Output
In/Output
Output
Output
Input
18
19
20
21
22-23
P35
N/C
GND
P32
P51-P50
Port 3, Pin 5
Not Connected
Ground
Port 3, Pin 2
Port 5, Pins 0,1
Output
Input
Input
Input
In/Output
PIN FUNCTIONS
XTAL1, XTAL2
Crystal 1, Crystal 2(time-based input and
output, respectively). These pins connect a parallel-
resonant crystal, ceramic resonator, LC, or any external
single-phase clock to the on-chip oscillator and buffer.
R//W
(output, write Low). The Read/Write signal is Low
when the MCU is writing to the external program or data
memory.
/RESET
(input, active Low). To avoid asynchronous and
noisy reset problems, the Z86C61/62/96 is equipped with
a reset filter of four external clocks (4TpC). If the external
/RESET signal is less than 4TpC in duration, no reset
occurs.
On the fifth clock after the /RESET is detected, an internal
RST signal is latched and held for an internal register count
of 18 external clocks, or for the duration of the external
/RESET, whichever is longer. During the reset cycle, /DS is
held active Low while /AS cycles at a rate of TpC/2. When
/RESET is deactivated, program execution begins at loca-
tion 000C (HEX). Reset time must be held Low for 50 ms,
or until V
CC
is stable, whichever is longer.
R//RL
(input, active Low). This pin when connected to
GND disables the internal ROM and forces the device to
function as a Z86C96 ROMless Z8. (
Note:
When left
unconnected or pulled High to V
the part functions as a
normal Z86C61/62 ROM version.) This pin is only available
on the 44-pin version of the Z86C61, and both versions of
the Z86C62.
/DS
(output, active Low). Data Strobe is activated once for
each external memory transfer. For a READ operation,
data must be available prior to the trailing edge of /DS. For
WRITE operations, the falling edge of /DS indicates that
output data is valid.
/AS
(output, active Low). Address Strobe is pulsed once
at the beginning of each machine cycle. Address out-
put is through Port 1 for all external programs. Memory
address transfers are valid at the trailing edge of /AS.
Under program control, /AS can be placed in the high-
impedance state along with Ports 0 and 1, Data Strobe,
and Read/Write.
Pin #
Symbol
Function
Direction
24-31
32
33-36
37-38
39-40
P07-P00
V
P55-P52
P11-P10
P57-P56
Port 0, Pins 0,1,2,3,4,5,6,7 In/Output
Power Supply
Port 5, Pins 2,3,4,5
Port 1, Pins 0,1
Port 5, Pins 6,7
Input
In/Output
In/Output
In/Output
41-46
47-48
49
50
51
P17-P12
P63-P62
P34
P33
GND
Port 1, Pins 2,3,4,5,6,7
Port 6, Pins 3,2
Port 3, Pin 4
Port 3, Pin 3
Ground
In/Output
In/Output
Output
Input
Input
52
53
54-55
56-57
58-63
/SYNC
SCLK
P21-P20
P61-P60
P27-P22
Synchronization
System Clock
Port 2, Pins 0,1
Port 6, Pins1,0
Port 2, Pins 2,3,4,5,6,7
Output
Output
In/Output
In/Output
In/Output
64-65
66
67
68
P41-P40
P31
P36
P42
Port 4, Pins 0,1
Port 3, Pin 1
Port 3, Pin 6
Port 4, Pin 2
In/Output
Input
Output
In/Output
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