參數(shù)資料
型號(hào)： Z86C96
廠商： ZiLOG, Inc.
英文描述： CMOS Z8 MICROCONTROLLER
中文描述： 單片機(jī)的CMOS Z8
文件頁(yè)數(shù)： 17/46頁(yè)
文件大?。?/td> 388K
代理商： Z86C96
17
Z86C61/62/96
Z8
M
ICROCONTROLLER
Port 3 can be configured under software control to provide
the following control functions: handshake for Ports 0 and
2 (/DAV and RDY); four external interrupt request signals
(IRQ3-IRQ0); timer input and output signals (T
IN
and T
OUT
),
and Data Memory Select (/DM).
D7
D6
D5
D4
D3
D2
D1
D0
Start Bit
Eight Data Bits
Transmitted Data (No Parity)
Two Stop Bits
SP
SP
ST
D7
D6
D5
D4
D3
D2
D1
D0
Start Bit
Eight Data Bits
Received Data (No Parity)
One Stop Bit
SP
ST
P
D6
D5
D4
D3
D2
D1
D0
Start Bit
Seven Data Bits
Transmitted Data (With Parity)
Odd Parity
Two Stop Bits
SP
SP
ST
P
D6
D5
D4
D3
D2
D1
D0
Start Bit
Seven Data Bits
Received Data (With Parity)
Parity Error Flag
One Stop Bit
ST
SP
Figure 14. Serial Data Formats
Table 7. Port 3 Pin Assignments
Pin
I/O
CTC1
Int.
P0 HS
P1 HS
P2 HS
UART
Ext
P30
P31
P32
P33
IN
IN
IN
IN
IRQ3
IRQ2
IRQ0
IRQ1
Serial In
T
IN
D/R
D/R
D/R
P34
P35
P36
P37
T0
T1
OUT
OUT
OUT
OUT
R/D
DM
R/D
T
OUT
R/D
Serial Out
IRQ4
IRQ5
Notes:
HS = Handshake Signals
D = Data Available
R = Ready
UART OPERATION
Port 3 lines P30 and P37, can be programmed as serial
I/O lines for full-duplex serial asynchronous receiver/
transmitter operation. The bit rate is controlled by the
Counter/Timer0.
The Z86C61/62/96 automatically adds a start bit and two
stop bits to transmitted data (Figure 14). Odd parity is also
available as an option. Eight data bits are always transmit-
ted, regardless of parity selection. If parity is enabled, the
eighth bit is the odd parity bit. An interrupt request (IRQ4)
is generated on all transmitted characters.
Received data must have a start bit, eight data bits and at
least one stop bit. If parity is on, bit 7 of the received data
is replaced by a parity error flag. Received characters
generate the IRQ3 interrupt request.
Note:
UART function is only available in stardard timing
mode (i.e., P01M D5 = 0).
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