參數(shù)資料
型號: Z86E43
廠商: ZiLOG, Inc.
英文描述: CMOS Z8 OTP Microcontroller(CMOS Z8系列一次可編程微控制器)
中文描述: 檢察官辦公室的CMOS Z8微控制器(的CMOS Z8系列一次可編程微控制器)
文件頁數(shù): 47/58頁
文件大?。?/td> 388K
代理商: Z86E43
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
DS97Z8X1500
P R E L I M I N A R Y
47
1
Permanent WDT.
When this feature is enabled, the WDT
is enabled after reset and will operate in Run and Halt
Mode. The control bits in the WDTMR do not affect the
WDT operation. If the clock source of the WDT is the inter-
nal RC oscillator, then the WDT will run in STOP mode. If
the clock source of the WDT is the XTAL1 pin, then the
WDT will not run in STOP mode.
Note:
WDT time-out in STOP Mode will not reset
SMR,SMR2,PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data
Registers, but will activate the Tpor delay.
WDTMR Register Accessibility.
The WDTMR register is
accessible only during the
first 60
internal system clock
cycles from the execution of the first instruction after
Power-On Reset, Watch-Dog reset or a STOP-Mode
Recovery (Figures 33 and 34). After this point, the register
cannot be modified by any means, intentional or
otherwise. The WDTMR cannot be read and is located in
Bank F of the Expanded Register File at address location
0FH.
Clock Free WDT Reset.
The WDT will enable the Z8 to
reset the I/O pins whenever the WDT times out, even with-
out a clock source running on the XTAL1 and XTAL2 pins.
WDTMR Bit D4 must be 0 for the clock Free WDT to work.
The I/O pins will default to their default settings
Figure 33. Watch-Dog Timer Mode Register
Write Only
D7
D6
D5
D4
D3
D2
D1
D0
WDTMR (F) 0F
WDT TAP INT RC OSC System Clock
00 5 ms 128 SCLK
01 10 ms 256 SCLK
10 20 ms 512 SCLK
11 80 ms 2048 SCLK
WDT During HALT
0 OFF
1 ON
*
WDT During STOP
0 OFF
1 ON
*
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
Reserved (Must be 0)
*
Default setting after RESET
*
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