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參數(shù)資料
| 型號(hào)： | Z86E83 |
| 廠(chǎng)商： | ZiLOG, Inc. |
| 英文描述： | CMOS Z8 Microcontroller(CMOS Z8系列微控制器) |
| 中文描述： | 微控制器的CMOS Z8的CMOS（Z8系列微控制器） |
| 文件頁(yè)數(shù)： | 41/52頁(yè) |
| 文件大?。?/td> | 338K |
| 代理商： | Z86E83 |
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Z86C83/C84/E83
CMOS Z8
MCU
Zilog
DS97DZ80700
P R E L I M I N A R Y
8-41
1
Stop-Mode Recovery Source (D2, D3, and D4).
These
three bits of the SMR register specify the wake-up source
of the STOP recovery (Figure 37 and Table 13). When the
Stop-Mode Recovery Sources are selected in this register
then SMR2 register bits D0,D1 must be set to zero. P33-
P31 and Port 2 cannot wake up from STOP Mode if the in-
put lines are configured as analog inputs to the Analog
comparator or Analog-to-Digital Converter.
Note:
If the Port 2 pin is configured as an output, this
output level will be read by the SMR circuitry.
Stop-Mode Recovery Delay Select (D5).
This bit, if High,
enables the T
POR
/RESET delay after Stop-Mode Recov-
ery. The default configuration of this bit is "1". A POR or
WDT reset will override the selection and cause the reset
delay to occur.
Stop-Mode Recovery Edge Select (D6).
A "1" in this bit
position indicates that a high level on the output to the ex-
clusive Or-Gate input from the selected recovery source
wakes the Z86C83/C84/E83 from STOP Mode. A "0" indi-
cates low-level recovery. The default is 0 on POR. This bit
is used for either SMR or SMR2.
Cold or Warm Start (D7).
This bit is set by the device
upon entering STOP Mode. A 0 in this bit (cold) indicates
that the device resets by POR/WDT reset. A "1" in this bit
(warm) indicates that the device awakens by a Stop-Mode
Recovery source.
Note:
A WDT reset out of STOP Mode will also set this bit
to a "1".
Stop-Mode Recovery Register 2 (SMR2).
This register
contains additional Stop-Mode Recovery sources. When
the Stop-Mode Recovery sources are selected in this reg-
ister then SMR Register Bits D2, D3, and D4 must be 0.
Table 13. Stop-Mode Recovery Source
SMR:432
D3
0
0
1
1
0
0
1
1
Operation
D2 Description of Action
0
POR and/or external reset recovery
1
Reserved
0
P31 transition (not in Analog Mode)
1
P32 transition (not in Analog Mode)
0
P33 transition (not in Analog Mode)
1
P27 transition
0
Logical NOR of P20 through P23
1
Logical NOR of P20 through P27
D4
0
0
0
0
1
1
1
1
Table 14. Stop-Mode Recovery Source
SMR:10
D1
0
0
1
Operation
Description of Action
POR and/or external reset recovery
Logical AND of P20 through P23
Logical AND of P20 through P27
D0
0
1
0
Figure 37. Stop-Mode Recovery Source
P31
P32
P33
P27
Stop-Mode Recovery Edge
Select (SMR)
P33 From Pads
Digital/Analog Mode
Select (P3M)
To P33 Data
Latch and IRQ1
To POR
/RESET
0 1 1
MUX
D4 D3 D2
1 1 0
D4 D3 D2
1 1 1
P20
P23
P20
P27
SMR2
SMR2
P20
P23
P20
P27
VDD
SMR2
VDD
SMR D4 D3 D2
0
0 0
D1 D0
1
0
D0
0
1
0
SMR
SMR
D4 D3 D2
1 0 1
SMR 0 1 0
D4 D3 D2
1 0 0
SMR
SMR
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