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參數(shù)資料
| 型號： | Z86E83 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CMOS Z8 Microcontroller(CMOS Z8系列微控制器) |
| 中文描述： | 微控制器的CMOS Z8的CMOS（Z8系列微控制器） |
| 文件頁數(shù)： | 42/52頁 |
| 文件大?。?/td> | 338K |
| 代理商： | Z86E83 |
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Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-42
P R E L I M I N A R Y
DS97DZ80700
Watch-Dog Timer Mode Register (WDTMR).
The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT is initially enabled by
executing the WDT instruction and refreshed on subse-
quent executions of the WDT instruction. The WDT circuit
is driven by an on-board RC oscillator or external oscillator
from the XTAL1 pin. The POR clock source is selected
with bit 4 of the WDT register (Figure 38).
WDT instruction affects the Z (Zero), S (Sign), and V
(Overflow) flags. The WDTMR must be written to within 64
internal system clocks. After that, the WDTMR is write pro-
tected.
Note:
WDT time-out while in Stop-Mode will not reset
SMR, PCON, WDTMR, P2M, P3M, Ports 2 and 3 Data
Registers, but will cause the reset delay to occur.
The Power-On Reset (POR) clock source is selected with
bit 4 of the WDTMR. Bits 0 and 1 control a tap circuit that
determines the time-out period. Bit 2 determines whether
the WDT is active during HALT and bit 3 determines WDT
activity during STOP. If bits 3 and 4 of this register are both
set to "1," the WDT is only driven by the external clock dur-
ing STOP Mode. This feature makes it possible to wake up
from STOP Mode from an internal source. Bits 5 through 7
of the WDTMR are reserved (Figure 39). This register is
accessible only during the first 60 processor cycles (60
SCLKs) from the execution of the first instruction after
Power-On-Reset, Watch-Dog Reset or a Stop-Mode Re-
covery. After this point, the register cannot be modified by
any means, intentional or otherwise. The WDTMR cannot
be read and is located in Bank F of the Expanded Register
group at address location 0FH.
Figure 38. Resets and WDT
CLK
18 Clock RESET
Generator
RESET
/Clear
WDT TAP SELECT
On Board
RC OSC.
CK
/CLR
128 SCLK
POR
256
SCLK
WDT/POR Counter Chain
512
SCLK
1024
SCLK
4096
SCLK
3.0V Operating
Voltage Det.
Internal
/RESET
WDT Select
(WDTMR)
CK Source
Select
(WDTMR)
XTAL
VCC
VLV
From Stop
Mode
Recovery
Source
/WDT
Stop Delay
Select (SMR D5)
12 ns Glitch Filter
+
-
M
U
X
/RESET
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z86E8300ZDP | 功能描述:插座和適配器 Z8 28 PIN DIP TO 28 PIN DIP ADAPTOR RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| Z86E8300ZDS | 功能描述:插座和適配器 Z8 28 PIN SOIC TO 28 PIN DIP ADAPTOR RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| Z86E8300ZDV | 功能描述:插座和適配器 PLCC-to-Dip Adaptor RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| Z86E8316PEC | 功能描述:8位微控制器 -MCU 4K OTP 16MHz W/ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| Z86E8316PEG | 功能描述:8位微控制器 -MCU 4K OTP 16MHz W/ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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