參數(shù)資料
型號: Z8S18033FSC
廠商: ZILOG INC
元件分類: 微控制器/微處理器
英文描述: CONN POWER HEADER 5ROW 10POS P-F
中文描述: 8-BIT, MICROPROCESSOR, PQFP80
封裝: QFP-80
文件頁數(shù): 49/70頁
文件大?。?/td> 387K
代理商: Z8S18033FSC
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DS971800401
P R E L I M I N A R Y
1-49
1
CLOCK MULTIPLIER REGISTER (Z180 MPU ADDRESS 1EH)
Bit 7.
X2 Clock Multiplier Mode. When this bit is set to 1,
this allows the programmer to double the internal clock
from that of the external clock. This feature will only oper-
ated effectively with frequencies of 10-16 MHz (20-32MHz
internal).
When
this
Z80180/Z8S180/Z8L180 device will operate in normal
mode. Upon powerup, this feature is disabled.
bit
is
set
to
0,
the
Bit 6.
Low Noise Crystal Option. Setting this bit to 1 will
enable the low noise option for the EXTAL and XTAL pins.
This option reduces the gain, in addition to reduction the
output drive capability to 30% of its original drive capability.
The Low Noise Crystal Option is recommended in the use
of crystals for PCMCIA applications where the crystal may
be driven too hard by the oscillator. Setting this bit to 0 will
select for normal operation of the EXTAL and XTAL pins.
The default for this bit is 0.
Note:
Operating restrictions for device operation are listed
below. If low noise option is required, and normal device
operation is needed, use the clock multiplier feature.
Figure 54. Clock Multiplier Register
1
1
1
0
0
1
7
6
5
4
3
2
1
1
0
1
RESERVED
LOW NOISE CRYSTAL
X2 CLOCK MULTIPLIER
Table 9. Low Noise Option
Low Noise
ADDR 1E, bit 6=1
20 MHz @ 4.5V, 100
°
C
10 MHz @ 3.0V, 100
°
C
Normal
ADDR 1E, bit 6=0
33 MHz @ 4.5V, 100
°
C
20 MHz @ 3.0V, 100
°
C
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