參數(shù)資料
型號(hào)： Z90103
廠商： ZiLOG, Inc.
英文描述： CAP 680PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014
中文描述： 40引腳低成本數(shù)字電視控制器
文件頁(yè)數(shù)： 6/36頁(yè)
文件大?。?/td> 232K
代理商： Z90103
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
6
DS97TEL1902
PIN DESCRIPTION
XTAL1, XTAL2.
These pins connect to the internal parallel-resonant clock
crystal (4 MHz max) oscillator circuit with two capacitors
to GND. XTAL1 is also used as an external clock input.
(time-based input, output, respectively).
SCLK System Clock.
It can be used to clock external glue logic.
SCLK is the internal system clock.
HSYNC
Sync is an input pin that accepts an externally generated
Horizontal Sync signal of either negative or positive polar-
ity.
(input, Schmitt triggered, CMOS level). Horizontal
VSYNC
Sync is an input pin that accepts an externally generated
Vertical Sync signal of either negative or positive polarity.
(input,Schmitt-triggered, CMOS level). Vertical
OSCIN, OSCOUT
tively). Oscillator input and output pins for on-screen dis-
play circuits. These pins connect to an inductor and two
capacitors to generate the character dot clock (typically
around 6 MHz). The dot clock frequency determines the
character pixel width and phase synchronized to HSYNC.
(Video Oscillator input, output, respec-
Vblank Video Blank
ble polarity. Used as a superimpose control port to display
characters from video RAM. The signal controls Y signal
output of the CRT and turns off the incoming video display
while the characters in video RAM are superimposed on
the screen. The red, green, and blue outputs drive the
three electron guns on the CRT directly, while the blank
output turns off the Y signal.
(output). CMOS output, programma-
Vblue Video Blue
eo signal (B-Y) and is programmable for either polarity.
(output). CMOS Output of the Blue vid-
Vgreen Video Green
video signal (G-Y) and is programmable for either polarity.
(output). CMOS Output of the Green
Vred Video Red
signal (R-Y) and is programmable for either polarity.
(output). CMOS Output of the Red video
Port 2
ble, bit programmable for either input or output. Input buff-
ers are Schmitt triggered. Bits programmed as outputs
may be globally programmed as either push pull or open-
drain (Figure 9).
(P27-P20). Port 2 is an 8-bit port, CMOS-compati-
Port 3
rectly. If appropriately enabled, a negative edge event is
latched in IRQ3 to initiate an IRQ3 vectored interrupt. An
application could place the device in STOP Mode when
P30 goes Low (in the IRQ3 interrupt routine). P30 initiates
a STOP Mode recovery when it subsequently goes to a
High. Port 3, P31 are read directly. If appropriately en-
abled, a negative edge event is latched in IRQ2 to initiate
an IRQ2 vectored interrupt. P31 High is signified as the
TIN signal to Timer1. Port 3, P34 and P35 are general-pur-
pose output lines. Port 3, P36 can be used as a general-
purpose output or as an output for TOUT (from Timer1 or
Timer2) or SCLK (Figure 10).
(P30, P31, P34-P36). Port 3, P30 input, is read di-
Port 6
CMOS compatible, input port. The outputs of the AFC
comparators internally feed into the Port 6, bit 6 and bit 7
inputs (Figure 11).
(P65-P60). Port 6 is a 6-bit, Schmitt triggered
AFCIN
put signal is supplied to two comparators with VTH1=2/5
V
CC
and VTH2=3/5 V
CC
typical threshold voltage. The
comparator outputs are internally connected to Port 6, bit
6 and bit 7. AFCIN is typically used to detect AFC voltage
level to accommodate digital automatic fine tuning func-
tions (Figure 12).
(Comparator input port, memory mapped). The in-
Pulse Width Modulator 1
as the D/A converter for Voltage Synthesis Tuning sys-
tems. It is a push-pull output with 14-bit resolution.
(PWM). PWM1 is typically used
Pulse Width Modulator 6-8
Pulse Width Modulators with 6-bit resolution.
(PWM). PWM8-PWM6 are
Pulse Width Modulator 9, 10, 11
Modulator circuits with 8-bit resolution. These PWMs are
12 volt, open-drain outputs.
(PWM). Pulse Width
Pulse Width Modulator 1, 6, 7, 8
grammed as general-purpose outputs. PWM 1 is 5 V
push-pull, and PWMs 6, 7, 8 are 12 volt open-drain out-
puts.
(PWM). Can be pro-
OH
/RESET
address 000CH after the /RESET pin is set to a high level.
The reset function is also carried out by detecting a V
transition state (automatic Power-On Reset) so that the
external reset pin can be permanently tied to V
level on /RESET forces a restart of the device.
System Reset. Code is executed from memory
CC
CC
. A low
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