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參數(shù)資料
| 型號(hào)： | Z9960 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer |
| 中文描述： | 2.5V/3.3V的，200兆赫多輸出零延遲緩沖器 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 253K |
| 代理商： | Z9960 |
Z9960
Document #: 38-07087 Rev. *C
Page 3 of 7
Overview
The Z9960 has an integrated PLL that provides low skew and
low jitter clock outputs for high-performance microprocessors.
Three independent banks of seven outputs as well as an
independent PLL feedback output, FB_OUT, provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the VCO is configured to
run between 200 MHz to 400 MHz. This allows a wide range
of output frequencies up to 200 MHz.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the input
reference clock set by FB_SEL select inputs; refer to
Table 1
.
The VCO frequency is then divided down to provide the
required output frequencies.
Zero Delay Buffer
When used as a zero delay buffer the Z9960 will likely be in a
nested clock tree application. For these applications the
Z9960 offers a low-voltage PECL clock input as a PLL
reference. This allows the user to use LVPECL as the primary
clock distribution device to take advantage of its far-superior
skew performance. The Z9960 then can lock onto the LVPECL
reference and translate with near zero delay to low skew
outputs.
By using one of the outputs as a feedback to the PLL, the
propagation delay through the device is eliminated. The PLL
works to align the output edge, with the input reference edge
thus producing a near-zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs. Because the static
phase offset is a function of the reference clock, the Tpd of the
Z9960 is a function of the configuration used.
Function Table
Control Pin
REF_SEL
AVDD
OE#
SELA
SELB
SELC
FB_SEL
0
1
TCLK
PLL Bypass, Outputs Controlled by OE#
Outputs Enabled
Output Bank A at VCO/2
Output Bank B at VCO/2
Output Bank C at VCO/2
Feedback Output at VCO/8
PECL_CLK
PLL Power
Outputs Disabled (except FB_OUT)
Output Bank A at VCO/4
Output Bank B at VCO/4
Output Bank C at VCO/4
Feedback Output at VCO/12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Z9960AL | SCR Thyristor; SCR Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:800V; On-State RMS Current, IT(rms):35A; Peak Non Repetitive Surge Current, Itsm:500A; Gate Trigger Current Max, Igt:40uA |
| Z9972 | 3.3V, 125-MHz, Multi-Output Zero Delay Buffer |
| Z9972AI | SCR Thyristor; SCR Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:800V; On-State RMS Current, IT(rms):40A; Peak Non Repetitive Surge Current, Itsm:520A; Gate Trigger Current Max, Igt:40uA |
| ZA2010 | PLASTIC CIGARETTE SOCKET |
| ZA2030 | AAM 30W Class-D Bridged Audio Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z9960AL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TWENTY-ONE DISTRIBUTED-OUTPUT CLOCK DRIVER|QFP|48PIN|PLASTIC |
| Z9972 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 125-MHz, Multi-Output Zero Delay Buffer |
| Z9972AI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MISCELLANEOUS CLOCK GENERATOR|QFP|52PIN|PLASTIC |
| Z9973 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 125-MHz, Multi-Output Zero Delay Buffer |
| Z9973BA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TWELVE DISTRIBUTED-OUTPUT CLOCK DRIVER|TQFP|52PIN|PLASTIC |
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