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參數(shù)資料
| 型號(hào)： | Z9960 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer |
| 中文描述： | 2.5V/3.3V的，200兆赫多輸出零延遲緩沖器 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 253K |
| 代理商： | Z9960 |
Z9960
Document #: 38-07087 Rev. *C
Page 4 of 7
Absolute Maximum Ratings
[2]
Input Voltage Relative to V
SS
:...............................V
SS
– 0.3V
Input Voltage Relative to V
DD
: ............................. V
DD
+ 0.3V
Storage Temperature: .................................-65
°
C to + 150
°
C
Operating Temperature:................................-40
°
C to + 85
°
C
Maximum ESD Protection................................................2kV
Maximum Power Supply:................................................5.5V
Maximum Input Current:
..................................................±
20mA
Note:
2. The voltage on any input or I/O or pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
IN
and V
OUT
should be constrained to
the range
V
SS
< (V
IN
or V
OUT
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Electrical Characteristics
V
DD
= 2.5V ±5%, T
A
= –40
°
C to +85
°
C
Parameter
V
IL[3]
V
IH[3]
V
PP
Description
Test Condition
Min.
V
SS
1.7
500
Typ.
–
–
–
Max.
0.7
V
DD
1000
Unit
V
V
mV
Input Low Voltage
Input High Voltage
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range
PECL_CLK
Input Low Current (@ V
IL
= V
SS
)
Input High Current (@ V
IH
=
V
DD
)
Output Low Voltage
Output High Voltage
Quiescent Supply Current
Input Pin Capacitance
VCMR
[4]
V
DD
–1.4
–
V
DD
–0.6
V
I
IL[5]
I
IH[5]
–
–
–
–
–120
120
μA
μA
V
OL[6]
V
OH[6]
I
DD
C
IN
I
OL
= 15 mA
I
OH
= –15 mA
V
DD
and AV
DD
–
–
–
10
4
0.6
V
V
1.8
–
–
13
–
mA
pF
DC Electrical Characteristics
V
DD
= 3.3V +5%, T
A
= –40
°
C to +85
°
C
Parameter
V
IL[3]
V
IH[3]
V
PP
Description
Test Condition
Min.
V
SS
2.0
500
Typ.
–
–
–
Max.
0.8
V
DD
1000
Unit
V
V
mV
Input Low Voltage
Input High Voltage
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range PECL_CLK
Input Low Current (@ V
IL
= V
SS
)
Input High Current (@ V
IH
= V
DD
)
Output Low Voltage
Output High Voltage
Quiescent Supply Current
Input Pin Capacitance
VCMR
[4]
I
IL[5]
I
IH[5]
V
OL[6]
V
OH[6]
I
DD
C
IN
Notes:
3. The LVCMOS inputs threshold is at 30% of V
.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when HIGH input is within the VCMR range
and the input lies within the V
specification.
5. Inputs have pull-up/pull-down resistors that affect input current.
6. Driving series or parallel terminated 50
(or 50
to V
DD
/2) transmission lines.
V
DD
–1.4
–
–
–
2.4
–
–
–
–
–
–
–
15
4
V
DD
–0.6
–120
120
0.55
–
20
–
V
μA
μA
V
V
mA
pF
I
OL
= 24 mA
I
OH
= –24 mA
V
DD
and AV
DD
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