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參數(shù)資料
| 型號(hào)： | ZL10100 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Power Quality Analyzer; Bandwidth Max:60Hz; Analyzer Features:6.50x18.00x14.00 inch; Spectrum Analyzer Type:Hand Held; Voltage Rating:600V RoHS Compliant: NA |
| 中文描述： | 單芯片合成變頻器的中頻放大器 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 414K |
| 代理商： | ZL10100 |
ZL10100
Data Sheet
4
Zarlink Semiconductor Inc.
1.0 Functional Description
The ZL10100 is a bipolar, broadband wide dynamic range mixer oscillator with on-board I2C bus controlled PLL
frequency synthesizer, optimized for application as the down converter in double conversion tuner systems. It also
has application in any system where a wide dynamic range broadband synthesized frequency converter is required.
The ZL10100 is a single chip solution containing all necessary active circuitry and simply requires an external
tuneable resonant network for the local oscillator sustaining network. The pin assignment is contained in the block
diagram in Figure 1 and the Pin Description in Figure 2.
1.1 Converter Section
In normal application the HIIF input is interfaced through appropriate impedance matching to the device input. The
RF input preamplifier of the device is designed for low noise figure, within the operating region of 1 to 1.3 GHz and
for high intermodulation distortion intercept so offering good signal to noise plus composite distortion spurious
performance when loaded with a multi carrier system. The preamplifier also provides gain to the mixer section and
back isolation from the local oscillator section. The typical RF input impedance and matching network for matching
to a 1220 MHz HIIF filter, type B1603 are contained in Figures 3 and 4.
The output of the preamplifier is fed to the mixer section which is optimized for low radiation application. In this
stage the RF signal is mixed with the local oscillator frequency, which is generated by the on-board oscillator. The
oscillator block uses an external tuneable network and is optimized for low phase noise. The typical application is
shown in Figure 6, and the phase noise performance in Figure 7. This block interfaces direct with the internal PLL to
allow for frequency synthesis of the local oscillator.
The output of the mixer is internally coupled to a differential IF amplifier, which provides further gain and provides
for a 150
, differential output impedance and drive capability. The IF amplifier allows for IF frequencies between
30 and 60 MHz.
The typical IF output impedance is contained in Figure 8.
The typical key performance data at 5 V Vcc and 25 deg C ambient are shown in the Quick Reference Data section
on Page 2.
1.2 Local Oscillator
To maximize the local oscillator phase noise performance, the application circuit as in Figure 5 must be carefully
adhered to including the component type and manufacture where applicable, strip line dimension and board
material. Any deviation from these parameters may adversely affect phase noise characteristics and so will require
re-optimization.
1.3 PLL frequency Synthesizer
The PLL frequency synthesizer section contains all the elements necessary, with the exception of a reference
frequency source and loop filter to control the oscillator, so forming a complete PLL frequency synthesized source.
The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which
enables the generation of a loop with good phase noise performance.
The LO signal from the oscillator drives an internal preamplifier, which provides gain and reverse isolation from the
divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider. The
programmable divider is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is 4-bits,
and the M counter is 11 bits.
The output of the programmable divider is fed to the phase comparator where it is compared in both phase and
frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal
controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to
the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in Table 1.
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| ZL10310 | Power Quality Recorder; Bandwidth Max:60Hz; Kit Contents:CTs, Voltage Leads, Ground Probes and Leads, PC Software and Download Cable; Voltage Rating:600V RoHS Compliant: NA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL10100/DDE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Single Chip Synthesized Downconverter with IF Amplifier |
| ZL10100/DDE1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Single Chip Synthesized Downconverter with IF Amplifier |
| ZL10100/DDF | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Single Chip Synthesized Downconverter with IF Amplifier |
| ZL10100/DDF1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Single Chip Synthesized Downconverter with IF Amplifier |
| ZL10100/LDF1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Single Chip Synthesized Downconverter with IF Amplifier |
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