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參數(shù)資料
| 型號： | ZL30106 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | SONET/SDH/PDH Network Interface DPLL |
| 中文描述： | 的SONET / SDH / PDH數(shù)字網(wǎng)絡(luò)接口全數(shù)字鎖相環(huán) |
| 文件頁數(shù)： | 1/48頁 |
| 文件大?。?/td> | 423K |
| 代理商： | ZL30106 |
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Synchronizes to clock-and-sync-pair to maintain
minimal phase skew between inputs and outputs
Supports output wander and jitter generation
specifications for SONET/SDH and PDH
interfaces
Accepts three input references and synchronizes
to any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
Provides a range of clock outputs:
-
2.048 MHz (E1), 16.384 MHz and either
4.096 MHz and 8.192 MHz or 32.768 MHz and
65.536 MHz
-
19.44 MHz (SONET/SDH)
-
1.544 MHz (DS1) and 3.088 MHz
-
a choice of 6.312 MHz (DS2), 8.448 MHz (E2),
44.736 MHz (DS3) or 34.368 MHz (E3)
Provides 5 styles of 8 kHz framing pulses and a
2 kHz multi-frame pulse
Provides automatic entry into Holdover and return
from Holdover
Manual and automatic hitless reference switching
Provides lock, holdover and accurate reference
fail indication
Selectable loop filter bandwidth of 29 Hz or
922 Hz
Less than 24 ps
rms
intrinsic jitter on the
19.44 MHz output clock, compliant with GR-253-
CORE OC-3 and G.813 STM-1 specifications
Less than 0.6 ns
pp
intrinsic jitter on all PDH output
clocks and frame pulses
Selectable external master clock source: clock
oscillator or crystal
Simple hardware control interface
Applications
Line card synchronization for SONET/SDH and
PDH systems
Wireless base-station Network Interface Card
AdvancedTCA and H.110 line cards
October 2004
Ordering Information
ZL30106QDG 64 pin TQFP
-40
°
C to +85
°
C
ZL30106
SONET/SDH/PDH
Network Interface DPLL
Data Sheet
Figure 1 - Functional Block Diagram
Reference
Monitor
Mode
Control
Virtual
Reference
IEEE
1149.1a
TIE
Corrector
Enable
State Machine
Frequency
Select
MUX
TIE
Corrector
Circuit
MODE_SEL1:0
TCK
RST
REF_SEL1:0
TIE_CLR
OSCo
OSCi
Master Clock
TDO
REF0
TDI TMS
TRST
HOLDOVER
HMS
LOCK
REF_FAIL0
REF_FAIL1
REF_FAIL2
APP_SEL1:0
DPLL
OUT_SEL2
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
REF2
E1
Synthesizer
DS1
Synthesizer
MUX
SDH
Synthesizer
Programmable
Synthesizer
C1.5o
C3o
C19o
F2ko
C6/8.4/34/44o
OUT_SEL1:0
BW_SEL
REF_SYNC0
REF1
REF_SYNC1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30106QDG | SONET/SDH/PDH Network Interface DPLL |
| ZL30107 | GbE Line Card Synchronizer |
| ZL30107GGG | GbE Line Card Synchronizer |
| ZL30107GGG2 | GbE Line Card Synchronizer |
| ZL30108LDA | Network Interface DPLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30106_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL |
| ZL30106QDG | 制造商:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH NETWORK INTRFC 64TQFP - Trays 制造商:Microsemi 功能描述:Microsemi ZL30106QDG Communication Misc |
| ZL30106QDG1 | 制造商:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH NETWORK INTRFC 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE SONET/SDH/PDH NTWK INTERFACEDPLL |
| ZL30107 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:GbE Line Card Synchronizer |
| ZL30107GGG | 制造商:Microsemi Corporation 功能描述: 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER ETH SGL 64CABGA 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER ETH SGL 64CABGA |
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