參數(shù)資料
型號: ZL30106
廠商: Zarlink Semiconductor Inc.
英文描述: SONET/SDH/PDH Network Interface DPLL
中文描述: 的SONET / SDH / PDH數(shù)字網(wǎng)絡(luò)接口全數(shù)字鎖相環(huán)
文件頁數(shù): 14/48頁
文件大?。?/td> 423K
代理商: ZL30106
ZL30106
Data Sheet
14
Zarlink Semiconductor Inc.
When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output
signal locked to the input signal. Each of the monitors has a build-in hysteresis to prevent flickering of the
REF_FAIL status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the
mode (Holdover/Normal) of the DPLL.
If the device is set to Automatic mode (MODE_SEL1:0=11), then the state machine does not immediately switch to
another reference. If the single cycle and/or coarse frequency failures persist for more than 50 ms or the precise
frequency monitor detects a failure, then the state machine will switch to another valid reference if that is available.
If there no other reference available, it stays in Holdover mode.
The precise frequency monitor’s failure thresholds are selected with the APP_SEL pins based on the ZL30106
applications. Figure 5, Figure 6 and Figure 7 show the out of range limits for various master clock accuracies. It will
take the precise frequency monitor up to 10 s to qualify or disqualify the input reference.
Figure 5 - Out-of-Range Thresholds for APP_SEL1:0=00
Figure 6 - Out-of-Range Thresholds for APP_SEL1:0=01
C20i Clock Accuracy
0 ppm
+32 ppm
-32 ppm
0
51
83
64
32
32
-32
-96
-75
-50
0
-25
25
75
Frequency offset [ppm]
Out of Range
Out of Range
Out of Range
In Range
In Range
In Range
C20
50
-64
-83
115
96
-32
-51
-115
C20
C20
100
-100
C20: 20 MHz master oscillator clock
C20i Clock
0 ppm
+4.6 ppm
-4.6 ppm
Accuracy
0
7.4
12
9.2
4.6
4.6
-4.6
-13.8
-15
-10
0
-5
5
15
Frequency offset [ppm]
Out of Range
Out of Range
Out of Range
In Range
In Range
In Range
C20
10
-9.2
-12
16.6
13.8
-4.6
-7.4
-16.6
C20
C20
C20: 20 MHz master oscillator clock
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