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參數(shù)資料
| 型號(hào)： | ZL30108LDG1 |
| 廠商： | XILINX INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MO-220, QFN-32 |
| 文件頁數(shù)： | 40/57頁 |
| 文件大?。?/td> | 691K |
| 代理商： | ZL30108LDG1 |
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ZL30108
Data Sheet
18
Zarlink Semiconductor Inc.
7.0
Applications
This section contains ZL30108 application specific details for power supply decoupling, clock and crystal operation,
reset operation,and control operation.
7.1
Power Supply Decoupling
Jitter levels on the ZL30108 output clocks may increase if the device is exposed to excessive noise on its power
pins. For optimal jitter performance, the ZL30108 device should be isolated from noise on power planes connected
to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note
ZLAN-178.
7.2
Master Clock
The ZL30108 can use either a clock or crystal as the master timing source. Zarlink Application Note ZLAN-68 lists a
number of applicable oscillators and crystals that can be used with the ZL30108.
7.2.1
Clock Oscillator
When selecting a Clock Oscillator, numerous parameters must be considered. These includes absolute frequency,
frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise.
The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30108 and the OSCo
output should be left open as shown in Figure 10.
Figure 10 - Clock Oscillator Circuit
1
Frequency
20 MHz
2
Tolerance
As required
3Rise & Fall Time
<10 ns
4
Duty Cycle
40% to 60%
Table 5 - Typical Clock Oscillator Specification
+3.3 V
20 MHz OUT
GND
0.1 F
+3.3 V
OSCo
ZL30108
OSCi
No Connection
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