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參數(shù)資料
| 型號： | ZL30108LDG1 |
| 廠商： | XILINX INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MO-220, QFN-32 |
| 文件頁數(shù)： | 57/57頁 |
| 文件大?。?/td> | 691K |
| 代理商： | ZL30108LDG1 |
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ZL30108
Data Sheet
9
Zarlink Semiconductor Inc.
Exceeding the threshold of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle
and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the
reference input signal when the failures are present for more than 2.5 s. The single cycle and coarse frequency
failures must be absent for 10 s to let the timer requalify the input reference signal as valid. Multiple failures of less
than 2.5 s each have an accumulative effect and will disqualify the reference. This is illustrated in Figure 4.
Figure 4 - Behavior of the Dis/Requalify Timer
When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output
signal locked to the input signal. Each of the monitors has a built-in hysteresis to prevent flickering of the REF_FAIL
status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the mode
(Holdover/Normal) of the DPLL.
Figure 5 - Out-of-Range Thresholds for OOR_SEL=1
2.5 s
10 s
current REF
timer
REF_FAIL
SCM or CFM failure
HOLDOVER
C20i Clock Accuracy
0 ppm
+32 ppm
-32 ppm
0
51
83
64
32
-32
-96
-75
-50
0
-25
25
75
Frequency offset [ppm]
Out of Range
In Range
C20
50
-64
-83
115
96
-32
-51
-115
C20
100
-100
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