參數(shù)資料
型號(hào)： ZL30120GGG
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA100
封裝： 9 X 9 MM, 0.80 MM PITCH, CABGA-100
文件頁(yè)數(shù)： 8/27頁(yè)
文件大?。?/td> 309K
代理商： ZL30120GGG
ZL30120
Data Sheet
8
Zarlink Semiconductor Inc.
G2
int_b
O
Interrupt Pin (LVCMOS).
Indicates a change of device status prompting the
processor to read the enabled interrupt service registers (ISR). This pin is an
open drain, active low and requires an external pulled up to VDD.
APLL Loop Filter
A6
apll_filter
A
External Analog PLL Loop Filter terminal.
B6
filter_ref0
A
Analog PLL External Loop Filter Reference.
C6
filter_ref1
A
Analog PLL External Loop Filter Reference.
JTAG and Test
J4
tdo
O
Test Serial Data Out (Output).
JTAG serial data is output on this pin on the
falling edge of tck. This pin is held in high impedance state when JTAG scan is
not enabled.
K2
tdi
I
u
Test Serial Data In (Input).
JTAG serial test instructions and data are shifted in
on this pin. This pin is internally pulled up to Vdd. If this pin is not used then it
should be left unconnected.
H4
trst_b
I
u
Test Reset (LVCMOS).
Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-
up to ensure that the device is in the normal functional state. This pin is internally
pulled up to Vdd. If this pin is not used then it should be connected to GND.
K3
tck
I
Test Clock (LVCMOS):
Provides the clock to the JTAG test logic. If this pin is not
used then it should be pulled down to GND.
J3
tms
I
u
Test Mode Select (LVCMOS).
JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
DD
. If this pin is not used
then it should be left unconnected.
Master Clock
K4
osci
I
Oscillator Master Clock Input (LVCMOS).
This input accepts a 20 MHz
reference from a clock oscillator (TCXO, OCXO). The stability and accuracy of
the clock at this input determines the free-run accuracy and the long term
holdover stability of the output clocks.
K5
osco
O
Oscillator Master Clock Output (LVCMOS).
This pin must be left unconnected
when the osci pin is connected to a clock oscillator.
Miscellaneous
A9
A10
B5
B9
B10
C5
D1
D3
G3
NC
No Connection.
Leave unconnected.
Pin #
Name
I/O
Type
Description
相關(guān)PDF資料
PDF描述
ZL30120GGG2 SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
ZL30121GGG2 SONET/SDH Low Jitter System Synchronizer
ZL30121 SONET/SDH Low Jitter System Synchronizer
ZL30121GGG SONET/SDH Low Jitter System Synchronizer
ZL30122 SONET/SDH Low Jitter Line Card Synchronizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL30120GGG2 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC LINE CARD SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC LINE CARD SYNCH 100CABGA
ZL30121 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:SONET/SDH Low Jitter System Synchronizer
ZL30121GGG 制造商:Microsemi Corporation 功能描述:SYS SYNCHRONIZER 100CABGA - Trays
ZL30121GGG2 制造商:Microsemi Corporation 功能描述:PB FREE LOW JITTER SYSTEM SYNCHRONIZER
ZL30121GGG2V2 制造商:Microsemi Corporation 功能描述:REV 2 PB FREE LOW JITTER SYSTEM SYNCHRO 制造商:Microsemi Corporation 功能描述:REV 2 PB FREE LOW JITTER SYSTEM SYNCHRO - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA
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