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參數(shù)資料
| 型號： | ZL30122GGG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH Low Jitter Line Card Synchronizer |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA64 |
| 封裝： | 9 X 9 MM, 1 MM PITCH, CABGA-64 |
| 文件頁數(shù)： | 1/23頁 |
| 文件大?。?/td> | 246K |
| 代理商： | ZL30122GGG |
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.
A full Design Manual is available to qualified customers.
To
register,
please
TimingandSync@Zarlink.com.
send
an
email
to
Features
Synchronizes with standard telecom system
references and synthesizes a wide variety of
protected telecom line interface clocks that are
compliant with Telcordia GR-253-CORE and ITU-T
G.813
Internal APLL provides standard output clock
frequencies up to 622.08 MHz with jitter < 3 ps
RMS suitable for GR-253-CORE OC-12 and G.813
STM-16 interfaces
Programmable output synthesizer generates clock
frequencies from any multiple of 8 kHz up to
77.76 MHz in addition to 2 kHz
Digital Phase Locked-Loop (DPLL) provides all the
features necessary for generating SONET/SDH
compliant clocks including automatic hitless
reference switching, automatic mode selection
(locked, free-run, holdover), and selectable loop
bandwidth
Provides 3 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
Provides 3 sync inputs for output frame pulse
alignment
Generates several styles of output frame pulses
with selectable pulse width, polarity, and frequency
Configurable input to output delay, and output to
output phase alignment
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
Supports IEEE 1149.1 JTAG Boundary Scan
May 2006
Figure 1 - Block Diagram
dpll_mod_sel
tck
tdo
tdi tms
trst_b
dpll_holdover
dpll_lock
sck
so
si
DPLL
rst_b
cs_b
diff_en
Reference
Monitors
ref
sync
ref0
ref1
ref2
sync0
sync1
sync2
int_b
sdh_clk
sdh_fp
p_clk
p_fp
ref2:0
sync2:0
ref_&_sync_status
Controller &
State Machine
SPI Interface
SONET/SDH
APLL
diff_clk_p/n
IEEE 1449.1
JTAG
Master
Clock
osco
osci
sdh_filter
filter_ref0
filter_ref1
Programmable
Synthesizer
ZL30122
SONET/SDH
Low Jitter Line Card Synchronizer
Data Sheet
Ordering Information
ZL30122GGG
ZL30122GGG2
64 Pin CABGA
64 Pin CABGA*
*Pb Free Tin/Silver/Copper
Trays
Trays
-40
o
C to +85
o
C
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30122GGG2 | 制造商:Microsemi Corporation 功能描述:PB FREE SONET/SDH PLL LINE CARD SYNCH. 制造商:Microsemi Corporation 功能描述:SONET/SDH LOW JITTER LINE CARD SYNCHRONIZER 64CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 64CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 64CABGA |
| ZL30123 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Low Jitter Line Card Synchronizer |
| ZL30123GGG | 制造商:Microsemi Corporation 功能描述:SONET/SDH LOW JITTER LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:Microsemi Corporation 功能描述:SONET/SDHPLLLINECARDSYNCHRONIZER 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA |
| ZL30123GGG2 | 制造商:Microsemi Corporation 功能描述:SONET/SDH LOW JITTER LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA |
| ZL30130GGG | 制造商:Microsemi Corporation 功能描述:OC-12 SONET/SDH 1GBE S2/S3E/S3/S4E SETS TIMING CARD - Trays 制造商:Zarlink Semiconductor Inc 功能描述:OC-12 SONET/SDH 1GBE S2/S3E/S3/S4E SETS TIMING CARD - Trays |
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