參數(shù)資料
型號(hào)： ZL30122GGG
廠(chǎng)商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： SONET/SDH Low Jitter Line Card Synchronizer
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA64
封裝： 9 X 9 MM, 1 MM PITCH, CABGA-64
文件頁(yè)數(shù)： 9/23頁(yè)
文件大?。?/td> 246K
代理商： ZL30122GGG
ZL30122
Data Sheet
9
Zarlink Semiconductor Inc.
1.0 Functional Description
The ZL30122 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and
synchronization for network interface cards. The DPLL is capable of locking to one of three input references and
provides a wide variety of synchronized output clocks and frame pulses.
1.1 DPLL Features
The Digital Phase-Locked Loop synchronizes to one of the qualified references and provides automatic or
manual hitless reference switching and a holdover function when no qualified references are available. It
provides a highly configurable set of features which are configurable through the serial interface. A summary of
these features are shown in Table 1.
Feature
DPLL
Modes of Operation
Free-run, Normal (locked), Holdover
User selectable: 14 Hz, 28 Hz, or wideband
1
(890 Hz / 56 Hz / 14 Hz)
Loop Bandwidth
1. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies equal to or
greater than 64 kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to or greater than 8 kHz and less than 64 kHz, the
loop bandwidth = 56 Hz. For reference frequencies equal to 2 kHz, the loop bandwidth is equal to 14 Hz.
Phase Slope Limiting
User selectable: 885 ns/s, 7.5
μ
s/s, 61
μ
s/s, or unlimited
Pull-in Range
Fixed: 130 ppm
Reference Inputs
Ref0, Ref1, Ref2
Sync Inputs
Sync0, Sync1, Sync2
Input Reference Frequencies
2 kHz, N * 8 kHz up to 77.76 MHz
Supported Sync Input
Frequencies
166.67 Hz, 400 Hz, 1 kHz, 2 kHz, 8 kHz, 64 kHz.
Input Reference
Selection/Switching
Automatic (based on programmable priority and revertiveness), or manual
selection
Hitless Reference Switching
Can be enabled or disabled
Output Clocks
diff_p/n, sdh_clk, p_clk
Output Frame Pulses
sdh_fp, p_fp synchronized to active sync reference.
Supported Output Clock
Frequencies
As listed in Table 4
Supported Output Frame
Pulse Frequencies
As listed in Table 4
External Pins Status
Indicators
Lock, Holdover
Table 1 - DPLL Features
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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ZL30123 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Low Jitter Line Card Synchronizer
ZL30123GGG 制造商:Microsemi Corporation 功能描述:SONET/SDH LOW JITTER LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:Microsemi Corporation 功能描述:SONET/SDHPLLLINECARDSYNCHRONIZER 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA
ZL30123GGG2 制造商:Microsemi Corporation 功能描述:SONET/SDH LOW JITTER LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA
ZL30130GGG 制造商:Microsemi Corporation 功能描述:OC-12 SONET/SDH 1GBE S2/S3E/S3/S4E SETS TIMING CARD - Trays 制造商:Zarlink Semiconductor Inc 功能描述:OC-12 SONET/SDH 1GBE S2/S3E/S3/S4E SETS TIMING CARD - Trays
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