參數(shù)資料
型號(hào): ZL30402/QCC1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80
封裝: 14 X 14 MM, 1.40 MM HEIGHT, MS-026BEC, LQFP-80
文件頁數(shù): 17/44頁
文件大小: 472K
代理商: ZL30402/QCC1
ZL30402
Data Sheet
24
Zarlink Semiconductor Inc.
Address: 11 H
Address: 13 H
Bit
Name
Functional Description
Default
7RSV
Reserved.
0
6RSV
Reserved.
0
5-3
C1.5POA2
to
C1.5POA0
C1.5 Phase Offset Adjustment. These three bits allow for changing of
the phase offset of the C1.5o clock relative to the active input reference.
The phase offset is an unsigned number in a range from 0 to 7. Each
increment by one represents phase-offset advancement by 80.96 ns.
Example: Writing 010 advances C1.5 clock by 162 ns. Successive writing
of 001 delays this clock by 80.96 ns from its present position
000
2-0
RSV
Reserved.
000
Table 11 - Control Register 3 (R/W)
Bit
Name
Functional Description
Default
7RSV
Reserved.
0
6RSV
Reserved.
0
5
C16dis
16.384 MHz Clock Disable. When set high, this bit tristates the 16.384 MHz clock
output.
0
4C8dis
8.192 MHz Clock Disable. When set high, this bit tristates the 8.192 MHz clock
output.
0
3C4dis
4.096 MHz Clock Disable. When set high, this bit tristates the 4.096 MHz clock
output.
0
2C2dis
2.048 MHz Clock Disable. When set high, this bit tristates the 2.048 MHz clock
output.
0
1
C1.5dis
1.544 MHz Clock Disable. When set high, this bit tristates the 1.544 MHz clock
output.
0
0RSV
Reserved.
0
Table 12 - Clock Disable Register 1 (R/W)
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