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參數(shù)資料
| 型號： | ZL30406 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | SONET/SDH Clock Multiplier PLL |
| 中文描述： | SONET / SDH的時鐘倍頻鎖相環(huán) |
| 文件頁數(shù)： | 14/21頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ZL30406 |
ZL30406
Data Sheet
14
Zarlink Semiconductor Inc.
: Voltages are with respect to ground unless otherwise stated.
:Typical figures are for design aid only: not guaranteed and not subject to production testing.
Note: Supply voltage and operating temperature are as per Recommended Operating Conditions
Note 1:
The I
LVPECL
current is determined by termination network connected to LVPECL outputs. More than 25% of this current flows
outside the chip and it does not contribute to the internal power dissipation.
LVPECL outputs terminated with Z
T
= 50
resistors biased to V
CC
-2V (see Figure 6)
Note 3:
CML outputs terminated with Z
T
= 50
resistors connected to low impedance DC bias voltage source (see Figure 7)
Note 2:
7
CMOS: Input bias current for
pulled-down inputs: FS1, FS2,
C77oEN-A, C77oEN-C,
C77oEN-D, OC-CLKoEN
I
B-PU
300
uA
V
I
= V
DD
8
CMOS: Input bias current for
pulled-up inputs: , C77oEN-B,
C19o_EN
I
B-PD
90
uA
V
I
= 0V
9
CMOS: High-level output
voltage
V
OH
2.4
V
I
OH
= 8 mA
10
CMOS: Low-level output
voltage
V
OL
0.4
V
I
OL
= 4 mA
11
CMOS: C19o output rise time
(18pF)
T
R
1.8
3.3
ns
18 pF load
12
CMOS: C19o output fall time
(18pF)
T
F
1.1
1.4
ns
18 pF load
13
LVPECL: Differential output
voltage
IV
OD_LVPECL
I
1.30
V
Note 2
14
LVPECL: Offset voltage
V
OS_LVPECL
Vcc-
1.38
Vcc-
1.27
Vcc-
1.15
V
Note 2
15
LVPECL: Output rise/fall times
T
RF
260
ps
Note 2
16
CML: Differential output
voltage
IV
OD_CML
I
0.70
V
Note 3
17
CML: Offset voltage (Also
referred to as common mode
voltage)
V
OS_CML
Vcc-
0.58
Vcc-
0.54
Vcc-
0.50
V
Note 3
18
CML: Output rise/fall times
T
RF
120
ps
Note 3
DC Electrical Characteristics
(continued)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
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