參數(shù)資料
型號(hào): ZL30406
廠商: Zarlink Semiconductor Inc.
英文描述: SONET/SDH Clock Multiplier PLL
中文描述: SONET / SDH的時(shí)鐘倍頻鎖相環(huán)
文件頁數(shù): 4/21頁
文件大?。?/td> 307K
代理商: ZL30406
ZL30406
Data Sheet
4
Zarlink Semiconductor Inc.
36
GND
Ground.
0 volt
37
NC
No internal bonding Connection. Leave unconnected.
38
GND
Ground.
0 volt
39
GND
Ground.
0 volt
40
NC
No internal bonding Connection. Leave unconnected.
41
GND
Ground.
0 volt
42
VDD
Positive Digital Power Supply.
+3.3 V ±10%
43
GND
Ground.
0 volt
44
VCC
Positive Analog Power Supply.
+3.3 V ±10%
45
GND
Ground.
0 volt
46
VDD
Positive Digital Power Supply.
+3.3 V ±10%
47
VCC
Positive Analog Power Supply.
+3.3 V ±10%
48
GND
Ground.
0 volt
49
VCC
Positive Analog Power Supply.
+3.3 V ±10%.
50
51
C77oN-D
C77oP-D
C77 Clock Output (LVPECL Output)
. These outputs provide a differential
LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated
to decrease supply current.
52
GND
Ground.
0 volt
53
VCC
Positive Analog Power Supply.
+3.3 V ±10%.
54
55
C77oP-C
C77oN-C
C77 Clock Output (LVPECL Output)
. These outputs provide a differential
LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated
to decrease supply current.
56
GND
Ground.
0 volt
57
VCC
Positive Analog Power Supply.
+3.3 V ±10%.
58
59
C77oN-B
C77oP-B
C77 Clock Output (LVPECL Output)
. These outputs provide a differential
LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated
to decrease supply current.
60
GND
Ground.
0 volt
61
VCC
Positive Analog Power Supply.
+3.3 V ±10%.
62
63
C77oP-A
C77oN-A
C77 Clock Output (LVPECL Output)
. These outputs provide a differential
LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated
to decrease supply current.
64
GND
Ground.
0 volt
65
EP_GND
Exposed die Pad Ground.
0 volt (connect to GND)
Pin Description Table (continued)
Pin #
Name
Description
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