參數(shù)資料
型號(hào)： ZL30409
廠商： Zarlink Semiconductor Inc.
英文描述： T1/E1 System Synchronizer with Stratum 3 Holdover
中文描述： T1/E1的系統(tǒng)同步與地層3緩繳暫繳稅
文件頁(yè)數(shù)： 30/32頁(yè)
文件大?。?/td> 483K
代理商： ZL30409
ZL30409
Data Sheet
30
Zarlink Semiconductor Inc.
See "Notes" following AC Electrical Characteristics tables.
Notes:
Voltages are with respect to ground (GND) unless otherwise stated.
Supply voltage and operating temperature are as per Recommended Operating Conditions.
Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
1. PRI reference input selected.
2. SEC reference input selected.
3. Normal Mode selected.
4. Holdover Mode selected.
5. Freerun Mode selected.
6. 8kHz Frequency Mode selected.
7. 1.544MHz Frequency Mode selected.
8. 2.048MHz Frequency Mode selected.
9. 19.44MHz Frequency Mode selected.
10. Master clock input OSCi at 20MHz
±
0ppm.
11. Master clock input OSCi at 20MHz
±
32ppm.
12. Master clock input OSCi at 20MHz
±
100ppm.
13. Selected reference input at
0ppm.
14. Selected reference input at
±
32ppm.
15. Selected reference input at
±
100ppm.
16. For Freerun Mode of
0ppm.
17. For Freerun Mode of
±
32ppm.
18. For Freerun Mode of
±
100ppm.
19. For capture range of
±
230ppm.
20. For capture range of
±
198ppm.
21. For capture range of
±
130ppm.
22. 25pF capacitive load.
23. OSCi Master Clock jitter is less than 2nspp, or 0.04UIpp where1UIpp=1/20MHz.
24. Jitter on reference input is less than 7nspp.
25. Applied jitter is sinusoidal.
26. Minimum applied input jitter magnitude to regain synchronization.
27. Loss of synchronization is obtained at slightly higher input jitter amplitudes.
28. Within 10ms of the state, reference or input change.
29. 1UIpp = 125us for 8kHz signals.
30. 1UIpp = 648ns for 1.544MHz signals.
31. 1UIpp = 488ns for 2.048MHz signals.
32. 1UIpp = 323ns for 3.088MHz signals.
33. 1UIpp = 244ns for 4.096MHz signals.
34. 1UIpp = 122ns for 8.192MHz signals.
35. 1UIpp = 61ns for 16.384MHz signals.
36. 1UIpp = 51.44ns for 19.44MHz signals.
37. No filter.
38. 40Hz to 100kHz bandpass filter.
39. With respect to reference input signal frequency.
40. After a RST or TCLR.
41. Master clock duty cycle 40% to 60%.
42. Prior to Holdover Mode, device was in Normal Mode and phase locked.
AC Electrical Characteristics - OSCi 20MHz Master Clock Input
Characteristics
Sym
Min
Max
Units
Conditions/Notes
1
Tolerance
-0
+0
ppm
16,19
2
-32
+32
ppm
17,20
3
-100
+100
ppm
18,21
4
Duty cycle
40
60
%
5
Rise time
10
ns
6
Fall time
10
ns
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ZL30409/DDA 制造商:Microsemi Corporation 功能描述:
ZL30409/DDB 制造商:Microsemi Corporation 功能描述:
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ZL30409/DDF 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:T1/E1 System Synchronizer with Stratum 3 Holdover
ZL30409_06 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:T1/E1 System Synchronizer with Stratum 3 Holdover
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