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參數(shù)資料
| 型號： | ZL30409 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | T1/E1 System Synchronizer with Stratum 3 Holdover |
| 中文描述： | T1/E1的系統(tǒng)同步與地層3緩繳暫繳稅 |
| 文件頁數(shù)： | 4/32頁 |
| 文件大?。?/td> | 483K |
| 代理商： | ZL30409 |
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ZL30409
Data Sheet
4
Zarlink Semiconductor Inc.
18
LOCK
Lock Indicator (CMOS Output).
This output goes high when the PLL is frequency locked to
the input reference.
19
C2o
Clock 2.048MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048Mb/s.
20
C4o
Clock 4.096MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048Mb/s
and 4.096Mb/s.
21
C19o
Clock 19.44MHz (CMOS Output).
This output is used in OC3/STS3 applications.
22
FLOCK
Fast Lock Mode (Input).
Set high to allow the PLL to quickly lock to the input reference
(less than 500 ms locking time).
24
IC
Internal Connection.
Tie low for normal operation.
25
C8o
Clock 8.192MHz (CMOS Output).
This output is used for ST-BUS operation at 8.192Mb/s.
26
C16o
Clock 16.384MHz (CMOS Output).
This output is used for ST-BUS operation with a
16.384MHz clock.
27
C6o
Clock 6.312 Mhz (CMOS Output).
This output is used for DS2 applications.
29
HOLD
OVER
Holdover (CMOS Output).
This output goes to a logic high whenever the PLL goes into
holdover mode.
30
PCCi
Phase Continuity Control Input (Input).
The signal at this pin affects the state changes
between Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode and
Secondary Normal Mode. See State Machine control section for details. The logic level at this
input is gated in by the rising edge of F8o.
32
NC
No connection.
Leave unconnected
33,34
IC
Internal Connection.
Connect to GND.
36
MS2
Mode/Control Select 2 (Input).
This input determines the state (Normal, Holdover or
Freerun) of operation. See Table 3 for details. The logic level at this input is gated in by the
rising edge of F8o
37
MS1
Mode/Control Select 1 (Input).
See MS2 pin description. The logic level at this input is gated
in by the rising edge of F8o. This pin is internally pulled down to GND.
38
RSEL
Reference Source Select (Input).
A logic low selects the PRI (primary) reference source as
the input reference signal and a logic high selects the SEC (secondary) input. The logic level
at this input is gated in by the rising edge of F8o. See Table 2. This pin is internally pulled
down to GND.
39
IC
Internal Connection.
Connect to GND.
40
FS2
Frequency Select 2 (Input).
This input, in conjunction with FS1, selects which of four
possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI and
SEC inputs. See Table 1.
41
FS1
Frequency Select 1 (Input).
See pin description for FS2.
42
IC
Internal Connection.
Connect to GND.
43
IC
Internal Connection.
Leave unconnected.
44
TDO
Test Serial Data Out (CMOS Output).
JTAG serial data is output on this pin on the falling
edge of TCK. This pin is held in high impedance state when JTAG scan is not enable.
Pin Description (continued)
Pin #
Name
Description
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| ZL30410 | CONN HDR INVERSE 30POS 5ROW VERT |
| ZL30410QCC | CONN SOCKET R/A 4R0W 24POS SLD |
| ZL30414 | SONET/SDH Clock Multiplier PLL |
| ZL30414QGC | SONET/SDH Clock Multiplier PLL |
| ZL30414QGC1 | SONET/SDH Clock Multiplier PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30409/DDA | 制造商:Microsemi Corporation 功能描述: |
| ZL30409/DDB | 制造商:Microsemi Corporation 功能描述: |
| ZL30409/DDE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 System Synchronizer with Stratum 3 Holdover |
| ZL30409/DDF | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 System Synchronizer with Stratum 3 Holdover |
| ZL30409_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 System Synchronizer with Stratum 3 Holdover |
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