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參數(shù)資料
| 型號： | ZL30414 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | SONET/SDH Clock Multiplier PLL |
| 中文描述： | SONET / SDH的時鐘倍頻鎖相環(huán) |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 421K |
| 代理商： | ZL30414 |
ZL30414
Data Sheet
12
Zarlink Semiconductor Inc.
3.2.3 CML to LVDS Interface
To configure the driver as an LVDS driver, external biasing resistors are required to set up the common mode
voltage as specified by ANSI/TIA/EIA-644 LVDS standard. The standard specifies the V
CM
(common mode voltage)
as minimum 1.125 V, typical 1.2 V, and maximum 1.375 V. The following figure provides a recommendation for
LVDS applications.
Figure 10 - LVDS Termination
3.2.4 CML to LVPECL Interface
The CML output can drive LVPECL input as is shown in Figure 11. The terminating resistors should be placed as
close as possible to the LVPECL receiver.
Figure 11 - CML to LVPECL Interface
ZL30414
CML
Driver
Z=50
Z=50
0.1 uF
+3.3 V
GND
VCC
LVDS
Receiver
10 nF
10 nF
R1
R2
VCC=+3.3 V
R1
R2
100
Typical resistor values: R1 = 16 k
,
R2 =
10 k
C155oP
C155oN
155.52 MHz
LVPECL
Receiver
CML
Driver
ZL30414
Z=50
Z=50
GND
Typical resistor values: R1 = 82
, R2 =130
R1
R2
VCC=+3.3 V
R1
R2
VCC
0.1 uF
+3.3 V
10 nF
10 nF
C155oP
C155oN
155.52 MHz
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| ZL30414QGC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
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| ZL30415 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
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