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參數(shù)資料
| 型號： | ZL30416 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | SONET/SDH Clock Multiplier PLL |
| 中文描述： | SONET / SDH的時鐘倍頻鎖相環(huán) |
| 文件頁數(shù)： | 1/22頁 |
| 文件大小： | 340K |
| 代理商： | ZL30416 |
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Low jitter clock outputs suitable for OC-192, OC-
48, OC-12, OC-3 and OC-1 SONET applications
as defined in Telcordia GR-253-CORE
Low jitter clock outputs suitable for STM-64, STM-
16, STM-4 and STM-1 applications as defined in
ITU-T G.813
Provides one differential LVPECL output clock
selectable to 19.44, 38.88, 77.76, 155.52 or
622.08 MHz
Provides a single-ended CMOS output clock at
19.44 MHz
Accepts a single-ended CMOS reference at
19.44 MHz or a differential LVDS, LVPECL or
CML reference at 19.44 or 77.76 MHz
Provides a LOCK indication
8 mm x 8 mm CABGA package
3.3 V supply
Applications
SONET/SDH line cards
Description
The ZL30416 is an Analog Phase-Locked Loop (APLL)
designed to provide jitter attenuation and rate
conversion for SDH (Synchronous Digital Hierarchy)
and
SONET
(Synchronous
networking equipment. The ZL30416 generates low
jitter output clocks suitable for Telcordia GR-253-
CORE OC-192, OC-48, OC-12, OC-3, and OC-1 and
ITU-T G.813 STM-64, STM-16, STM-4 and STM-1
applications.
Optical
Network)
The ZL30416 accepts a CMOS compatible reference
at 19.44 MHz or a differential LVDS, LVPECL or CML
reference at 19.44 or 77.76 MHz and generates a
differential LVPECL output clock selectable to 19.44,
38.88, 77.76, 155.52 or 622.08 MHz and a single-
ended CMOS clock at 19.44 MHz. The ZL30416
provides a lock indication.
November 2004
Ordering Information
ZL30416GGG 64 Ball CABGA
-40
°
C to +85
°
C
ZL30416
SONET/SDH Clock Multiplier PLL
Data Sheet
Figure 1 - Functional Block Diagram
Frequency
& Phase
Detector
VCO
Frequency
Dividers
and
Clock
Drivers
LPF
OC-CLKoP/N
VCC
GND
VDD
C19o
FS2
Loop
Filter
BIAS
19.44 MHz and 77.76 MHz
State
Machine
LOCK
Reference
and
Bias Circuit
C19o, C38o, C77o,
C155o, C622o,
LVPECL output
C19i
Reference
Selection
MUX
REF_SEL
REF_FREQ
REFinP/N
C19oEN
C19i or C77i
CML, LVDS,
LVPECL input
FS3
FS1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30416_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30416GGG | 制造商:Microsemi Corporation 功能描述:PLL CLOCK MLTPLR SGL 64CABGA - Trays 制造商:Microsemi Corporation 功能描述:SONET / SDH CLOCK MULTIPLIER PLL 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC PLL SONET/SDH CLK MULT 64CBGA 制造商:Microsemi Corporation 功能描述:IC PLL SONET/SDH CLK MULT 64CBGA |
| ZL30416GGG2 | 制造商:Microsemi Corporation 功能描述:PB FREE SONET / SDH CLOCK MULTIPLIER PLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC PLL SONET/SDH CLK MULT 64CBGA 制造商:Microsemi Corporation 功能描述:IC PLL SONET/SDH CLK MULT 64CBGA |
| ZL30461 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:COMPACT STRATUM 3 TIMING MODULE |
| ZL30461MGG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:COMPACT STRATUM 3 TIMING MODULE |
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