- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373784 > ZL30414QGC1 (ZARLINK SEMICONDUCTOR INC) SONET/SDH Clock Multiplier PLL PDF資料下載
參數(shù)資料
| 型號(hào)： | ZL30414QGC1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH Clock Multiplier PLL |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026, TQFP-64 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 421K |
| 代理商： | ZL30414QGC1 |
ZL30414
Data Sheet
3
Zarlink Semiconductor Inc.
11
BIAS
Bias.
See Figure 13 for the recommended bias circuit.
12
C155oEN
C155o Clock Enable (CMOS Input).
If tied high this control pin enables the
C155oP/N differential driver. Pulling this input low disables the output clock and
deactivates differential drivers.
13
C622oEN-A
C622 Clock Output Enable A (CMOS Input).
If tied high this control pin
enables the C622oP/N-A output clock. Pulling this input low disables the output
clock without deactivating differential drivers.
14
C622oEN-B
C622 Clock Output Enable B (CMOS Input).
If tied high this control pin
enables the C622oP/N-B output clock. Pulling this input low disables the output
clock without deactivating differential drivers.
15
C622oEN-C
C622 Clock Output Enable C (CMOS Input).
If tied high this control pin
enables the C622oP/N-C output clock.Pulling this input low disables the output
clock without deactivating differential drivers.
16
C622oEN-D
C622 Clock Output Enable D (CMOS Input).
If tied high this control pin
enables the C622oP/N-D output clock.Pulling this input low disables the output
clock without deactivating differential drivers.
17
GND
Ground.
0 volt
18
VDD
Positive Digital Power Supply.
+3.3 V ±10%
19
NC
No internal bonding Connection.
Leave unconnected.
20
NC
No internal bonding Connection.
Leave unconnected.
21
NC
No internal bonding Connection.
Leave unconnected.
22
VDD
Positive Digital Power Supply.
+3.3 V ±10%
23
IC
Internal Connection.
Connect this pin to Ground (GND).
24
NC
No internal bonding Connection.
Leave unconnected.
25
NC
No internal bonding Connection.
Leave unconnected.
26
C19oEN
C19o Output Enable (CMOS Input).
If tied high this control pin enables the
C19o output clock. Pulling this pin low forces output driver into a high
impedance state.
27
GND
Ground.
0 volt
28
C19i
C19 Reference Input (CMOS Input).
This pin is a single-ended input reference
source used for synchronization. This pin accepts 19.44 MHz.
29
VDD
Positive Digital Power Supply.
+3.3 V ±10%
30
GND
Ground.
0 volt
31
VDD
Positive Digital Power Supply.
+3.3 V ±10%
32
GND
Ground.
0 volt
Pin Description Table (continued)
Pin #
Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30415 | SONET/SDH Clock Multiplier PLL |
| ZL30415GGC | SONET/SDH Clock Multiplier PLL |
| ZL30416 | SONET/SDH Clock Multiplier PLL |
| ZL30416GGG | SONET/SDH Clock Multiplier PLL |
| ZL38001DGA | Low-Voltage Acoustic Echo Canceller with Low ERL Compensation |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30414QGG1 | 制造商:Microsemi Corporation 功能描述:PB FREE SONET/SDH CLOCK MULTIPLIER PLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC PLL SONET/SDH CLK MULT 64TQFP 制造商:Microsemi Corporation 功能描述:IC PLL SONET/SDH CLK MULT 64TQFP |
| ZL30415 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30415_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30415GGC | 制造商:Microsemi Corporation 功能描述:SONET / SDH CLOCK MULTIPLIER PLL 制造商:Microsemi Corporation 功能描述:PLL CLOCK MLTPLR SGL 64CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC PLL SONET/SDH CLK MULT 64CBGA 制造商:Microsemi Corporation 功能描述:IC PLL SONET/SDH CLK MULT 64CBGA 制造商:ZARLINK 功能描述: |
| ZL30415GGF | 制造商:Microsemi Corporation 功能描述:SONET / SDH CLOCK MULTIPLIER PLL - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC PLL SONET/SDH CLK MULT 64CBGA 制造商:Microsemi Corporation 功能描述:IC PLL SONET/SDH CLK MULT 64CBGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。