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參數(shù)資料
| 型號： | ZL38002QDG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Low-Voltage Acoustic Echo Canceller With Noise Reduction |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, LEAD FREE, MS-026ABC, TQFP-48 |
| 文件頁數(shù)： | 14/47頁 |
| 文件大?。?/td> | 440K |
| 代理商： | ZL38002QDG1 |
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ZL38002
Data Sheet
14
Zarlink Semiconductor Inc.
In SSI operation, the frame boundary is determined by the rising edge of the ENA1 enable strobe (see Figure 7).
The other enable strobe (ENA2) is used for parsing input/output data and it must pulse within 125 microseconds of
the rising edge of ENA1.
In SSI operation, the enable strobes may be a mixed combination of 8 or 16 BCLK cycles allowing the flexibility to
mix 2’s complement linear data on one port (e.g., Rin/Sout) with companded data on the other port (e.g., Sin/Rout).
Table 3 - SSI Enable Strobe Pins
2.3 PCM Law and Format Control (LAW, FORMAT)
The PCM companding/coding law used by the ZL38002 is controlled through the LAW and FORMAT pins. ITU-T
G.711 companding curves for m-Law and A-Law are selected by the LAW pin. PCM coding ITU-T G.711 and Sign-
Magnitude are selected by the FORMAT pin. See Table 4.
Figure 7 - SSI Operations
Enable Strobe Pin
Designated PCM I/O Port
ENA1
Line Side Echo Path (PORT 1)
ENA2
Acoustic Side Echo Path (PORT 2)
BCLK
ENA1
Rin
Sout
8 or 16 bits
8 or 16 bits
PORT1
PORT2
8 or 16 bits
8 or 16 bits
ENA2
Sin
Rout
Note that the two ports are independent so that, for example, PORT1 can operate with 8-bit enable strobes and PORT2 can operate
with 16-bit enable strobes.
outputs = High impedance
inputs = don’t care
start of frame (SSI)
EC
EC
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