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參數(shù)資料
| 型號(hào)： | ZL38002QDG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Low-Voltage Acoustic Echo Canceller With Noise Reduction |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, LEAD FREE, MS-026ABC, TQFP-48 |
| 文件頁(yè)數(shù)： | 24/47頁(yè) |
| 文件大?。?/td> | 440K |
| 代理商： | ZL38002QDG1 |
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ZL38002
Data Sheet
24
Zarlink Semiconductor Inc.
Register Table 5 - High Pass Filter Constant Register (FLTSH)
Register Table 6 - Mu Constant Register
Bit
Name
Description
7-5
F
R
2-F
R
0
F
S
4-F
S
0
These four bits control the cut-off frequency of HPF at Rin.
4-0
These four bits control the cut-off frequency of HPF at Sin.
Bit
Name
Description
7-0
MU5-0
This register allows the user to program control the adaptation speed. This
register allows a maximum value of 3Fh. The default value is 08h
corresponding to decimal value of 2.0. Decimal value of 1.0 is 04h. Lower
values correspond to slower adaptation speed.
Reserved. Write’0’.
Read/Write Page 0, Address: 04
H
Reset Value: A1
H
7
6
5
4
3
2
1
0
FR2
FR1
FR0
FS4
FS3
FS2
FS1
FS0
3 dB frequency and bit 0-4 for Sin
00: 2 KHz; 08: 2.65 Hz; 10: 3 KHz; 18: 3.6 Hz
01: 820 Hz; 09: 1.1 KHz; 11: 1.2 KHz; 19: 1.6 KH
02: 350 Hz; 0A: 450 Hz; 12: 580 Hz; 1A: 700 Hz
03: 160 Hz; 0B: 200 Hz; 13: 250 Hz; 1B: 300 Hz
04: 80 Hz; 0C: 100 Hz; 14: 125 Hz; 1C: 150 Hz
05: 40 Hz; 0D: 50 Hz; 15: 60 Hz; 1D: 70 Hz
06: 20 Hz; 0E: 25 Hz; 16: 30 Hz; 1E: 38 Hz
07: 10 Hz; 0F: 14 Hz; 17: 15 Hz; 1F: 18 Hz
3dB frequency and bit 5-7 for Rin
0: 2 KHz; 1; 820 Hz; 2: 350 Hz; 3: 160 Hz; 4: 80 Hz; 5: 40 Hz; 6: 20 Hz; 7: 10 Hz
Read/Write Page 0, Address:05
H
Reset Value: 08
H
7
6
5
4
3
2
1
0
RESV
RESV
MU
5
MU
4
MU
3
MU
2
MU
1
MU
0
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