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ZL38065
Data Sheet
39
Zarlink Semiconductor Inc.
Power-up
00
hex
Main Control Register 1 (EC Group 1)
Page0
A12=0
A11=0
R/W Address: 401
hex
R/W Address: 402
hex
R/W Address: 403
hex
R/W Address: 404
hex
R/W Address: 405
hex
R/W Address: 406
hex
R/W Address: 407
hex
R/W Address: 408
hex
R/W Address: 409
hex
R/W Address: 40A
hex
R/W Address: 40B
hex
R/W Address: 40C
hex
R/W Address: 40D
hex
R/W Address: 40E
hex
R/W Address: 40F
hex
Bit 1
Law
Main Control Register 2 (EC Group 1)
Main Control Register 3 (EC Group 1)
Main Control Register 4 (EC Group 1)
Main Control Register 5 (EC Group 1)
Main Control Register 6 (EC Group 1)
Main Control Register 7 (EC Group 1)
Main Control Register 8 (EC Group 1)
Main Control Register 9 (EC Group 1)
Main Control Register 10 (EC Group 1)
Main Control Register 11 (EC Group 1)
Main Control Register 12 (EC Group 1)
Main Control Register 13 (EC Group 1)
Main Control Register 14 (EC Group 1)
Main Control Register 15 (EC Group 1)
Bit 5
Unused
Unused
Functional Description of Register Bits
Unused bits
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control
Register 2. When low, the Tone Detector B Interrupt is active.
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control
Register 2. When low, the Tone Detector A Interrupt is active.
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept ITU-T
(G.711) PCM code. When low, both Echo Cancellers A and B for a given group, accept sign-
magnitude PCM code.
A/
μ
Law: When high, both Echo Cancellers A and B for a given group, accept A-Law
companded PCM code. When low, both Echo Cancellers A and B for a given group, accept
μ
-
Law companded PCM code.
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group,
are active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are
placed in Power Down mode. In this mode, the corresponding PCM data are bypassed from
Rin to Rout and from Sin to Sout with two frames delay. When the PWUP bit toggles from
zero to one, the echo cancellers A and B execute their initialization routine which presets their
registers, Base Address+00
hex
to Base Address+3F
hex
, to default Reset Value and clears the
Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute
properly. Once the initialization routine is executed, the user can set the per channel Control
Registers for their specific application.
Bit 7
Unused
Bit 6
Bit 4
MTDBI
Bit 3
MTDAI
Bit 2
Format
Bit 0
PWUP
Unused
MTDBI
MTDAI
Format
Law
PWUP