參數(shù)資料
型號: ZL50015GAC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 1 K Digital Switch with Stratum 4E DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA256
封裝: 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256
文件頁數(shù): 10/122頁
文件大?。?/td> 926K
代理商: ZL50015GAC
ZL50015
Data Sheet
10
Zarlink Semiconductor Inc.
Changes Summary
The following table captures the changes from the October 2004 issue.
Page
Item
Change
38, 70, 72
Section 12.1, “DPLL Timing Modes“ on
page 38
RCCR Register bits “FDM1 - 0” on page 70
RCCR Register bits “DPM1 - 0” on page 72
The on-chip DPLL’s normal, holdover, automatic,
and freerun modes are now collectively referred
to as DPLL timing modes instead of operation
modes. This change is to avoid confusion with
the two main device operating modes; the
master and slave modes.
39
12.1.3.1, “Automatic Reference Switching
Without Preferences“ and 12.1.3.2,
“Automatic Reference Switching With
Preferences“
Added two new sections, Section 12.1.3.1 and
Section 12.1.3.2 to clarify the DPLL’s automatic
reference switching with and without preference
operations in Automatic Timing Mode.
68
Table 31, Lock Detector Threshold
Register (LDTR) Bits
Clarified threshold calculations.
70
Table 34, Reference Change Control
Register (RCCR) Bits
Added description to clarify that only two
consecutive references can be used in
automatic timing mode with a preferred
reference.
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