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參數(shù)資料
| 型號： | ZL50023QCC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Enhanced 4 K Digital Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQFP256 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, MS-026BJC, LQFP-256 |
| 文件頁數(shù)： | 39/80頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | ZL50023QCC |
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ZL50023
Data Sheet
39
Zarlink Semiconductor Inc.
0
MBPS
Memory Block Programming Start:
A zero to one transition of this bit starts the memory block programming function. The
MBPS and BPD2 - 0 bits in this register must be defined in the same write operation.
Once the MBPE bit in the Control Register is set to high, the device requires two
frames to complete the block programming. After the programming function has fin-
ished, the MBPS bit returns to low, indicating the operation is completed. When MBPS
is high, MBPS or MBPE can be set to low to abort the programming operation.
Whenever the microprocessor writes a one to the MBPS bit, the block programming
function is started. As long as this bit is high, the user must maintain the same logical
value to the other bits in this register to avoid any change in the device setting.
Bit
Name
Description
15 - 2
Unused
Reserved
In normal functional mode, these bits
MUST
be set to zero.
1
SRSTSW
Software Reset Bit for Switch
When this bit is low, switching blocks are in normal operation. When this bit is high,
switching blocks are in software reset state. Refer to Table 12, “Address Map for
Registers (A13 = 0)” on page 32 for details regarding which registers are affected.
0
Unused
Reserved
In normal functional mode, these bits
MUST
be set to zero.
Table 16 - Software Reset Register (SRR) Bits
Bit
Name
Description
Table 15 - Internal Mode Selection Register (IMS) Bits (continued)
External Read/Write Address: 0001
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
STIO_
PD_EN
BDH
BDL
RBER
EN
TBER
EN
BPD
2
BPD
1
BPD
0
MBPS
External Read/Write Address: 0002
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SRST
SW
0
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