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參數(shù)資料
| 型號： | ZN447E |
| 英文描述： | Converter IC |
| 中文描述： | 轉(zhuǎn)換器IC |
| 文件頁數(shù)： | 3/18頁 |
| 文件大小： | 289K |
| 代理商： | ZN447E |
ZN448/9
3
ELECTRICAL CHARACTERISTICS
(Cont.)
V
IN
= +4V, V
= MAX
V
IN
= +0.8V, V
CC
= MAX
V
IN
= +2.4V, V
CC
= MAX
V
IN
= +0.4V, V
CC
= MAX
V
IN
= +2.4V, V
CC
= MAX
V
IN
= +0.4V, V
CC
= MAX
I
OH
= +2.4V, V
CC
= MAX
I
OL
= +0.4V, V
CC
= MAX
V
OUT
= +2V
-
-
-
0.9
500
4
-
-
-
2
-
-
-
2
-
-
-
2.4
-
-
-
-
-
-
180
60
80
60
200
-
-
+0.5
-
-
-
-
-
-
-
-
-
300
±
10
-
-
+150
-300
-
-
-
-
-
-
180
210
80
110
80
-
-
1
-
2
1
-
-
0.8
800
-500
-
0.8
-
-
-
0.8
-
-
-
0.4
-100
1.6
2
-1.5
250
260
100
140
100
-
250
Min.
Typ.
Max.
MHz
%/
°
C
k
MHz
ns
V
V
μ
A
μ
A
V
V
μ
A
μ
A
V
V
μ
A
μ
A
V
V
μ
A
mA
μ
A
V
ns
ns
ns
ns
ns
ns
ns
Parameter
Units
Conditions
Clock
On-chip clock frequency
Clock frequency temperature coefficient
Clock resistor
Maximum external clock frequency
Clock pulse width
High level input voltage V
IH
Low level input voltage V
IL
High level input current I
IH
Low level input current I
IL
Logic
(over operating temperature range)
Convert input
High level input voltage V
IH
Low level input voltage V
IL
High level input current I
IH
Low level input current I
IL
RD
input
High level input voltage V
IH
Low level input voltage V
IL
High level input current I
IH
Low level input current I
IL
High level output voltage V
OH
Low level output voltage V
OL
High level output current I
OH
Low level output current I
OL
Three-state disable output leakage
Input clamp diode voltage
RD
input to data output
Enable/disable delay times T
E1
T
E0
T
D1
T
D0
Convert pulse width t
WR
WR
input to
BUSY
output
GENERAL CIRCUIT OPERATION
The ZN448/9 utilises the successive approximation
technique. Upon receipt of a negative-going pulse at the
WR
input the
BUSY
output goes low, the MSB is set to 1 and all
other bits are set to 0, which produces an output voltage of
V
from the DAC. This is compared to the input voltage V
;
a decision is made on the next negative clock edge to reset the
MSB to 0 if V
IN
or leave it set to 1 if < V
IN
.
2
Bit 2 is set to 1 on the same clock edge, producing an output
V
2
from the DAC of 4
of the MSB. This voltage is compared to V
and on the next
clock edge a decision is made regarding bit 2, whilst bit 3 is set
to 1. This procedure is repeated for all eight bits. On the eighth
negative clock edge
BUSY
goes high indicating that the
conversion is complete.
REF
V
REF
2
V
REF
V
REF
4
During a conversion the RD input will normally be held high to
keep the three-state buffers in their high impedance state.
Data can be read out by taking
RD
low, thus enabling the
three-state output. Readout is non-destructive.
CONVERSION TIMING
The ZN448/9 will accept a low-going CONVERT pulse, which
can be completely asynchronous with respect to the clock,
and will produce valid data between 7.5 and 8.5 clock pulses
later depending on the relative timing of the clock and
CONVERT signals. Timing diagrams for the conversion are
shown in Fig.3.
The converter is cleared by a low-going CONVERT pulse,
which sets the most significant bit and results all the other bits
and the
BUSY
flag. Whilst the CONVERT input is low the MSB
output of the DAC is continuously compared with the analogue
input, but otherwise the converter is inhibited.
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