參數(shù)資料
型號: μPD434004
廠商: NEC Corp.
英文描述: 4M-Bit CMOS Fast Static RAM(4M位CMOS 快速靜態(tài))
中文描述: 4分位CMOS快速靜態(tài)隨機(jī)存儲器(4分位的CMOS快速靜態(tài))
文件頁數(shù): 7/14頁
文件大?。?/td> 98K
代理商: ΜPD434004
7
μ
PD434004
Write Cycle
μ
PD434004LE-20
μ
PD434004LE-25
Parameter
Symbol
Unit
Condition
MIN.
MAX .
MIN.
MAX .
Write cycle time
t
WC
20
25
ns
CS to end of write
t
CW
14
17
ns
Address valid to end of write
t
AW
14
17
ns
Write pulse width
t
WP
12
15
ns
Data valid to end of write
t
DW
10
12
ns
Data hold time
t
DH
0
0
ns
Address setup time
t
AS
0
0
ns
Write recovery time
t
WR
3
3
ns
WE to output in high impedance
t
WHZ
8
10
ns
Note
Output active from end of write
t
OW
0
0
ns
Note
See the output load shown in
Fig. 2
.
Write Cycle Timing Chart 1 (WE Controlled)
#
t
WC
t
AS
t
WP
t
AW
t
WR
Data in
Address (Input)
CS (Input)
WE (Input)
I/O
(Input/Output)
t
CW
t
WHZ
t
DW
t
DH
t
OW
Indefinite data out
Indefinite
data out
High im-
pedance
High im-
pedance
Caution CS or WE should be fixed to high level during address transition.
Remark 1.
Write operation is done during the overlap time of a low level CS and a low level WE.
2.
When WE is at low level, I/O pins are always high impedance. When WE is at high level, read
operation is executed. Therefore OE should be at high level to make I/O pins high impedance.
3.
t
WR
is measured between rising edge of CS or WE, whichever occurs first, and end of t
WC
.
4.
t
WHZ
is measured at V
OL
+ 200 mV and V
OH
– 200 mV with the output load shown in
Fig.2
.
5.
t
OW
is measured at
±
200 mV from steady-state voltage with the output load shown in
Fig.2
.
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μPD434008 4M-Bit CMOS Fast Static RAM(4M位CMOS 快速靜態(tài))
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