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參數(shù)資料
| 型號： | μPD703008 |
| 廠商： | NEC Corp. |
| 英文描述： | 16/32 Bit RISC Microcontrollers(16/32位RISC微控制器) |
| 中文描述： | 16/32位RISC微控制器（16/32位的RISC微控制器） |
| 文件頁數(shù)： | 133/141頁 |
| 文件大?。?/td> | 374K |
| 代理商： | ΜPD703008 |
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121
APPENDIX A INSTRUCTION MNEMONIC (IN ALPHABETICAL ORDER)
Table A-1. Instruction Mnemonic (in alphabetical order) (6/7)
Instruction
Mnemonic
Operand
Format
CY
OV
S
Z
SAT
Instruction Function
SLD.B
disp7 [ep], reg2
IV
–
–
–
–
–
Byte load. Adds the 7-bit displacement, zero-
extended to word length, to the element pointer to
generate a 32-bit address. Byte data is read
from the generated address, sign-extended to
word length, and stored to reg2.
SLD.H
disp8 [ep], reg2
IV
–
–
–
–
–
Half-word load. Adds the 8-bit displacement,
zero-extended to word length, to the element
pointer to generate a 32-bit address. Half-word
data is read from this 32-bit address with bit 0
masked to 0, sign-extended to word length, and
stored to reg2.
SLD.W
disp8 [ep], reg2
IV
–
–
–
–
–
Word load. Adds the 8-bit displacement, zero-
extended to word length, to the element pointer to
generate a 32-bit address. Word data is read
from this 32-bit address with bits 0 and 1 masked
to 0, and stored to reg2.
SST.B
reg2, disp7 [ep]
IV
–
–
–
–
–
Byte store. Adds the 7-bit displacement, zero-
extended to word length, to the element pointer to
generate a 32-bit address, and stores the data of
the lowest byte of reg2 to the generated address.
SST.H
reg2, disp8 [ep]
IV
–
–
–
–
–
Half-word store. Adds the 8-bit displacement,
zero-extended to word length, to the element
pointer to generate a 32-bit address, and stores
the lower half-word of reg2 to the generated 32-
bit address with bit 0 masked to 0.
SST.W
reg2, disp8 [ep]
IV
–
–
–
–
–
Word store. Adds the 8-bit displacement, zero-
extended to word length, to the element pointer to
generate a 32-bit address, and stores the word
data of reg2 to the generated 32-bit address with
bits 0 and 1 masked to 0.
ST.B
reg2, disp16 [reg1]
VII
–
–
–
–
–
Byte store. Adds the 16-bit displacement, sign-
extended to word length, to the data of reg1 to
generate a 32-bit address, and stores the lowest
byte data of reg2 to the generated address.
ST.H
reg2, disp16 [reg1]
VII
–
–
–
–
–
Half-word store. Adds the 16-bit displacement,
sign-extended to word length, to the data of reg1
to generate a 32-bit address, and stores the
lower half-word of reg2 to the generated 32-bit
address with bit 0 masked to 0.
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