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參數(shù)資料
| 型號： | μPD70P3002 |
| 廠商： | NEC Corp. |
| 英文描述： | 16/32 Single -Chip Microcontroller(16/32 位單片微控制器) |
| 中文描述： | 16/32單片機(jī)（16/32位單片微控制器） |
| 文件頁數(shù)： | 32/56頁 |
| 文件大?。?/td> | 367K |
| 代理商： | ΜPD70P3002 |
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μ
PD70P3002
32
(5) Read timing (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
CLKOUT
↑→
address delay time
<20>
t
DKA
3
20
ns
CLKOUT
↑→
address float delay time
<21>
t
FKA
3
15
ns
CLKOUT
↓→
ASTB delay time
<22>
t
DKST
3
15
ns
CLKOUT
↑
→
DSTB delay time
<23>
t
DKD
3
15
ns
CLKOUT
↑→
status delay time
<24>
t
DKS
3
15
ns
Data input setting time (to CLKOUT
↑
)
<25>
t
SIDK
5
ns
Data input hold time (from CLKOUT
↑
)
<26>
t
HKID
5
ns
WAIT setting time (to CLKOUT
↓
)
<27>
t
SWTK
5
ns
WAIT hold time (from CLKOUT
↓
)
<28>
t
HKWT
5
ns
Address hold time (from CLKOUT
↑
)
<29>
t
HKA
0
ns
Address setting time (to ASTB
↓
)
<30>
t
SAST
0.5T – 10
ns
Address hold time (from ASTB
↓
)
<31>
t
HSTA
0.5T – 10
ns
DSTB
↓→
address float delay time
<32>
t
FDA
0
ns
Data input setting time (to address)
<33>
t
SAID
(2 + n)T – 20
ns
Data input setting time (to DSTB
↓
)
<34>
t
SDID
(1 + n)T – 20
ns
ASTB
↓→
DSTB
↓
delay time
<35>
t
DSTD
0.5T – 10
ns
Data input hold time (from DSTB
↑
)
<36>
t
HDID
0
ns
DSTB
↑→
address output delay time
<37>
t
DDA
(1 + i)T
ns
DSTB
↑→
ASTB
↑
delay time
<38>
t
DDSTH
0.5T – 10
ns
DSTB
↑→
ASTB
↓
delay time
<39>
t
DDSTL
(1.5 + i)T – 10
ns
Status setting time (to ASTB
↓
)
<40>
t
SSST
0.5T – 10
ns
Status hold time (from ASTB
↑
)
<41>
t
HSTS
0.5T – 10
ns
DSTB width, low
<42>
t
WDL
(1 + n)T – 10
ns
ASTB width, high
<43>
t
WSTH
T – 10
ns
WAIT setting time (to address)
<44>
t
SAWT1
n
≥
1
1.5T – 20
ns
<45>
t
SAWT2
(1.5 + n)T – 20
ns
WAIT hold time (from address)
<46>
t
HAWT1
n
≥
1
(0.5 + n)T
ns
<47>
t
HAWT2
(1.5 + n)T
ns
WAIT setting time (to ASTB
↓
)
<48>
t
SSTWT1
n
≥
1
T – 15
ns
<49>
t
SSTWT2
(1 + n)T – 15
ns
WAIT hold time (from ASTB
↓
)
<50>
t
HSTWT1
n
≥
1
nT
ns
<51>
t
HSTWT2
(1 + n)T
ns
Remarks 1.
T = t
CYK
2.
n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when
the programmable wait state is inserted.
3.
i indicates the number of idle states (0 or 1) to be inserted in the read cycle.
4.
Be sure to observe at least one of data input hold times t
HKID
(<26>) and t
HDID
(<36>).
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